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    APPARATUS AND METHOD FOR INTERPOLATING BETWEEN A FIRST SIGNAL AND A SECOND SIGNAL
    1.
    发明申请
    APPARATUS AND METHOD FOR INTERPOLATING BETWEEN A FIRST SIGNAL AND A SECOND SIGNAL 审中-公开

    公开(公告)号：WO2019117932A1

    公开(公告)日：2019-06-20

    申请号：PCT/US2017/066555

    申请日：2017-12-15

    Applicant: INTEL IP CORPORATION

    Inventor： DEGANI, Ofir ,  BANIN, Rotem ,  BEN-BASSAT, Assaf ,  ASA, Gil ,  KHAMAISI, Bassam

    IPC: H03L7/099 ,  H03L7/081 ,  G04F10/00

    Abstract: An apparatus for interpolating between a first signal and a second signal is provided. The apparatus includes a first plurality of interpolation cells configured to generate a first interpolation signal at a first node. At least one of the first plurality of interpolation cells is configured to supply, based on a first number of bits of a control word, at least one of the first signal and the second signal to the first node. The apparatus further includes a second plurality of interpolation cells configured to generate a second interpolation signal at a second node. At least one of the second plurality of interpolation cells is configured to supply, based on a second number of bits of the control word, at least one of the first signal and the second signal to the second node. The apparatus additionally includes an interpolation circuit configured to weight the second interpolation signal based on a weighting factor, and to combine the first interpolation signal and the weighted second interpolation signal to generate a third interpolation signal.

    APPARATUS, SYSTEM AND METHOD OF GENERATING A FREQUENCY OUTPUT WITH A DIGITALLY CONTROLLED RING OSCILLATOR (DCRO)
    2.
    发明申请
    APPARATUS, SYSTEM AND METHOD OF GENERATING A FREQUENCY OUTPUT WITH A DIGITALLY CONTROLLED RING OSCILLATOR (DCRO) 审中-公开
    用数字控制环形振荡器（DCRO）产生频率输出的装置，系统和方法

    公开(公告)号：WO2018063231A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2016/054392

    申请日：2016-09-29

    Applicant: INTEL IP CORPORATION

    Inventor： RAVI, Ashoke ,  BANIN, Rotem ,  DEGANI, Ofir ,  BEN-HAIM, David ,  KALMANOVICH, Yigal

    IPC: H03L7/099

    CPC classification number: H03L7/0995 ,  H03L7/093 ,  H03L2207/50 ,  H04L7/0331 ,  H04L7/08

    Abstract: For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.

    Abstract translation: 例如，数字PLL可以包括被配置为基于控制信号生成频率输出的数字控制的环形振荡器（DCRO），DCRO包括循环次序的多个级，第一 所述多级的级包括由所述控制信号控制的多个逆变器模块，并且所述多级包括多个输出，所述多个输出用于驱动所述多级中的多个第二级的输入; 解码器，用于基于DCRO的多个级的多个采样相位来解码DCRO的相位; 以及相位误差估计器，用于基于DCRO的相位和频率控制字估计相位误差，控制信号基于相位误差。

    CALIBRATION OF DYNAMIC ERROR IN HIGH RESOLUTION DIGITAL-TO-TIME CONVERTERS
    3.
    发明申请
    CALIBRATION OF DYNAMIC ERROR IN HIGH RESOLUTION DIGITAL-TO-TIME CONVERTERS 审中-公开
    高分辨率数字时间转换器中的动态误差校准

    公开(公告)号：WO2017052876A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2016/047982

    申请日：2016-08-22

    Applicant: INTEL IP CORPORATION

    Inventor： RAVI, Ashoke ,  DEGANI, Ofir ,  BANIN, Rotem ,  BEN-BASSAT, Assaf

    IPC: G04F10/00 ,  H03K5/135 ,  H03M1/10 ,  H03M1/82

    CPC classification number: H04L7/042 ,  G04F10/005 ,  H03K5/135 ,  H03M1/1061 ,  H03M1/82 ,  H04B1/0475 ,  H04L7/0054

    Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.

    Abstract translation: 校准系统用于校准或校正包括检测器部件和失真校正部件的数字 - 时间转换器（DTC）。 DTC可以通过基于数字代码控制一个或多个信号的偏移来接收一个或多个信号和数字代码以产生调制信号。 检测器部件可以包括TDC或另一个DTC，其操作以响应于检测到调制信号的非线性来测量动态特性。 失真校正组件可以生成一组基于测量从DTC的输出消除动态特性的失真数据。

    CIRCUIT, APPARATUS, DIGITAL PHASE LOCKED LOOP, RECEIVER, TRANSCEIVER, MOBILE DEVICE, METHOD AND COMPUTER PROGRAM TO REDUCE NOISE IN A PHASE SIGNAL
    4.
    发明申请
    CIRCUIT, APPARATUS, DIGITAL PHASE LOCKED LOOP, RECEIVER, TRANSCEIVER, MOBILE DEVICE, METHOD AND COMPUTER PROGRAM TO REDUCE NOISE IN A PHASE SIGNAL 审中-公开
    电路，设备，数字锁相环，接收机，收发机，移动设备，方法和计算机程序以降低相位信号中的噪声

    公开(公告)号：WO2017153852A1

    公开(公告)日：2017-09-14

    申请号：PCT/IB2017/050361

    申请日：2017-01-24

    Applicant: INTEL IP CORPORATION

    Inventor： BANIN, Elan ,  MAROM, Tamar ,  HOROVITZ, Gil ,  BANIN, Rotem

    IPC: H03H11/12

    CPC classification number: H03L7/091 ,  H03L7/085 ,  H04L7/0331 ,  H04L7/048

    Abstract: A circuit (10) is configured to reduce a noise component of a measured phase signal. The circuit (10) comprises an input (12) for a phase signal of an oscillator and an error signal estimator (14) configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit (20) further comprises a combiner (16) configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.

    Abstract translation: 电路（10）被配置为减小测量的相位信号的噪声分量。 电路（10）包括用于振荡器的相位信号的输入（12）和被配置为基于奇偶校验信息确定相位信号中的奇偶校验信息和估计的误差幅度的误差信号估计器（14）。 所述电路（20）还包括组合器（16），所述组合器被配置为基于所述相位信号和所估计的误差幅度的组合来向所述测量的相位信号提供所述降低的噪声分量。

    AN APPARATUS AND A METHOD FOR GENERATING A RADIO FREQUENCY SIGNAL
    6.
    发明申请
    AN APPARATUS AND A METHOD FOR GENERATING A RADIO FREQUENCY SIGNAL 审中-公开
    一种用于产生无线电频率信号的装置和方法

    公开(公告)号：WO2017051216A1

    公开(公告)日：2017-03-30

    申请号：PCT/IB2015/057375

    申请日：2015-09-25

    Applicant: INTEL IP CORPORATION

    Inventor： SIEVERT, Sebastian ,  DEGANI, Ofir ,  RAVI, Ashoke ,  BANIN, Rotem

    IPC: H04L27/36

    CPC classification number: H04L27/362

    Abstract: An apparatus for generating a radio frequency signal based on a symbol within a constellation diagram is provided. The constellation diagram is spanned by a first axis representing an in-phase component and an orthogonal second axis representing a quadrature component. The apparatus includes a processing unit configured to select a segment of a plurality of segments of the constellation diagram containing the symbol. The segment is delimited by a third axis and a fourth axis each crossing the origin of the constellation diagram and spanning an opening angle of the segment of less than about 90°. The processing unit is further configured to calculate a first coordinate of the symbol with respect to the third axis, and a second coordinate of the symbol with respect to the fourth axis. The apparatus further includes a plurality of digital-to-analog converter cells configured to generate the radio frequency signal using the first coordinate and the second coordinate.

    Abstract translation: 提供了一种基于星座图内的符号生成射频信号的装置。 星座图由表示同相分量的第一轴和表示正交分量的正交第二轴跨越。 该装置包括：处理单元，被配置为选择包含符号的星座图的多个段的段。 该段由第三轴和第四轴限定，每个轴和第四轴各自与星座图的原点相交，并跨越小于约90°的段的开度角。 处理单元还被配置为计算相对于第三轴的符号的第一坐标和相对于第四轴的符号的第二坐标。 该装置还包括被配置为使用第一坐标和第二坐标产生射频信号的多个数模转换器单元。

    DETERMINISTIC JITTER REMOVAL USING A CLOSED LOOP DIGITAL-ANALOG MECHANISM
    9.
    发明申请
    DETERMINISTIC JITTER REMOVAL USING A CLOSED LOOP DIGITAL-ANALOG MECHANISM 审中-公开

    公开(公告)号：WO2018118274A1

    公开(公告)日：2018-06-28

    申请号：PCT/US2017/061506

    申请日：2017-11-14

    Applicant: INTEL IP CORPORATION

    Inventor： HOROVITZ, Gil ,  BANIN, Elan ,  KUSHNIR, Igal ,  FARBER, Aryeh ,  KRICHMAN, Ran ,  DEGANI, Ofir ,  BANIN, Rotem

    IPC: H03L7/06 ,  H03L7/085 ,  H03L7/08 ,  H03K5/156

    Abstract: A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.

    DEVICE AND METHOD TO REDUCE POWER AMPLIFIER POWER CONSUMPTION
    10.
    发明申请
    DEVICE AND METHOD TO REDUCE POWER AMPLIFIER POWER CONSUMPTION 审中-公开
    降低功率放大器功率消耗的装置和方法

    公开(公告)号：WO2018063661A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2017/049053

    申请日：2017-08-29

    Applicant: INTEL IP CORPORATION

    Inventor： KERNER, Michael ,  PERLMUTTER, Uri ,  FRIEDMAN, Avishay ,  BANIN, Rotem ,  MAIMON, Tzvi

    IPC: H04L27/26 ,  H04L5/00

    Abstract: A wireless device and method of power consumption reduction are generally described herein. The wireless device may map a plurality of data symbols to sub-carriers for an orthogonal frequency division multiplexing (OFDM) transmission. The wireless device may divide the plurality of data symbols into first and second groups of data symbols. The wireless device may generate a first OFDM signal from the first group of data symbols for amplification by a first power amplifier (PA). The wireless device may generate a second OFDM signal from the second group of data symbols for amplification by a second PA. The data symbols of the first and second groups may be selected to provide a PAPR of the first OFDM signal that is lower than a PAPR of a composite OFDM signal based on the plurality of data symbols.

    Abstract translation: 本文中一般描述了无线设备和降低功耗的方法。 无线设备可以将多个数据符号映射到副载波以用于正交频分复用（OFDM）传输。 无线设备可以将多个数据符号分成第一和第二组数据符号。 无线设备可以从第一组数据符号生成第一OFDM信号以供第一功率放大器（PA）放大。 无线设备可以从第二组数据符号生成第二OFDM信号以供第二PA放大。 可以选择第一和第二组的数据符号以提供第一OFDM信号的PAPR，其低于基于多个数据符号的复合OFDM信号的PAPR。

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