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    MAJORITY LOGIC GATE BASED SEQUENTIAL CIRCUIT
    2.
    发明申请
    MAJORITY LOGIC GATE BASED SEQUENTIAL CIRCUIT 审中-公开

    公开(公告)号：WO2022139890A1

    公开(公告)日：2022-06-30

    申请号：PCT/US2021/048762

    申请日：2021-09-01

    Applicant: KEPLER COMPUTING, INC.

    Inventor： MANIPATRUNI, Sasikanth ,  FANG, Yuan-Sheng ,  MENEZES, Robert ,  DOKANIA, Rajeev Kumar ,  RAMESH, Ramamoorthy ,  MATHURIYA, Amrita

    IPC: H03K19/23 ,  H03K3/037

    Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.

    LOW POWER FERROELECTRIC BASED MAJORITY LOGIC GATE ADDER
    4.
    发明申请
    LOW POWER FERROELECTRIC BASED MAJORITY LOGIC GATE ADDER 审中-公开

    公开(公告)号：WO2021133988A1

    公开(公告)日：2021-07-01

    申请号：PCT/US2020/066963

    申请日：2020-12-23

    Applicant: KEPLER COMPUTING INC.

    Inventor： MANIPATRUNI, Sasikanth ,  FANG, Yuan-Sheng ,  MENEZES, Robert ,  DOKANIA, Rajeev Kumar ,  THAREJA, Gaurav ,  RAMESH, Ramamoorthy ,  MATHURIYA, Amrita

    IPC: H03K19/23 ,  H03K19/094 ,  G06F7/501 ,  H01L28/55 ,  H01L28/65

    Abstract: An adder uses with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5 -input majority gate. Other inputs to the 5-input majority gate are the same as those of the 3 -input majority gate. The output of the 5 -input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals to the majority gates can be analog, digital, or a combination of them, which are driven to first terminals of non- ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate.

    MAJORITY LOGIC GATE WITH NON-LINEAR INPUT CAPACITORS
    6.
    发明申请
    MAJORITY LOGIC GATE WITH NON-LINEAR INPUT CAPACITORS 审中-公开

    公开(公告)号：WO2022246340A1

    公开(公告)日：2022-11-24

    申请号：PCT/US2022/070445

    申请日：2022-01-31

    Applicant: KEPLER COMPUTING INC.

    Inventor： MANIPATRUNI, Sasikanth ,  RIOS, Rafael ,  REYNOLDS, Neal ,  ODINAKA, Ikenna ,  MENEZES, Robert ,  DOKANIA, Rajeev Kumar ,  RAMESH, Ramamoorthy ,  MATHURIYA, Amrita

    IPC: H03K19/23 ,  H03K19/00

    Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

    3D INTEGRATED ULTRA HIGH-BANDWIDTH MEMORY
    8.
    发明申请
    3D INTEGRATED ULTRA HIGH-BANDWIDTH MEMORY 审中-公开

    公开(公告)号：WO2020242781A1

    公开(公告)日：2020-12-03

    申请号：PCT/US2020/032974

    申请日：2020-05-14

    Applicant: KEPLER COMPUTING INC.

    Inventor： DOKANIA, Rajeev Kumar ,  MANIPATRUNI, Sasikanth ,  MATHURIYA, Amrita ,  OLAOSEBIKAN, Debo

    IPC: H01L23/495 ,  H01L23/34 ,  H01L23/498 ,  H01L21/768 ,  H01L27/108

    Abstract: A packaging technology to improve performance of an AI processing system. An IC package includes: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.

    ARTIFICIAL INTELLIGENCE PROCESSOR WITH THREE-DIMENSIONAL STACKED MEMORY
    9.
    发明申请
    ARTIFICIAL INTELLIGENCE PROCESSOR WITH THREE-DIMENSIONAL STACKED MEMORY 审中-公开

    公开(公告)号：WO2020190440A1

    公开(公告)日：2020-09-24

    申请号：PCT/US2020/018875

    申请日：2020-02-19

    Applicant: KEPLER COMPUTING INC.

    Inventor： MANIPATRUNI, Sasikanth ,  DOKANIA, Rajeev Kumar ,  MATHURIYA, Amrita ,  RAMESH, Ramamoorthy

    IPC: G06F15/78 ,  H01L27/02 ,  G06N3/06

    Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises RAM such as a ferroelectric RAM (FeRAM), SRAM, or DRAM having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

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