公开(公告)号：WO2015038328A1

公开(公告)日：2015-03-19

申请号：PCT/US2014/052763

申请日：2014-08-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CASTRO, Hernan

IPC: G11C11/21 ,  H01L27/115

CPC classification number: G11C13/003 ,  G06F3/061 ,  G06F3/0658 ,  G06F3/0673 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0088 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77

Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.

Abstract translation: 用于在交叉点阵列中并行访问存储器单元的方法和结构包括并行地访问设置在第一选定列和第一选定行之间的第一存储器单元和布置在与第一选定列不同的第二选定列之间的第二存储单元 列和与第一选定行不同的第二选定行。 并行访问包括同时在第一所选列和第一选定行之间以及在第二选定列与第二选定行之间应用访问偏移。 在小区处于阈值状态或小区处于阈值后恢复周期时，并行进行访问。

公开(公告)号：WO2013026044A1

公开(公告)日：2013-02-21

申请号：PCT/US2012/051489

申请日：2012-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HIRST, Jeremy ,  CASTRO, Hernan ,  TANG, Stephan

IPC: G11C7/10 ,  G11C5/14

CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0059 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2207/063

Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

Abstract translation: 本文公开的示例主题涉及用于其中的装置和/或装置和/或其中使用的各种方法，其中响应于已经发生快速恢复事件的确定，电路的电位的施加可以被启动并随后改变 在电路中。 例如，电路可以包括作为所施加的电势的结果可能经历回跳事件的存储器单元。 在某些示例实现中，可以提供感测电路，其响应于在存储器单元中发生的快速恢复事件以产生反馈信号，以启动施加到存储器单元的电位的变化。