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    ELECTRONIC DEVICE, MEMORY CELL, AND METHOD OF FLOWING ELECTRIC CURRENT
    1.
    发明申请
    ELECTRONIC DEVICE, MEMORY CELL, AND METHOD OF FLOWING ELECTRIC CURRENT 审中-公开
    电子设备，存储器单元以及流过电流的方法

    公开(公告)号：WO2016126375A1

    公开(公告)日：2016-08-11

    申请号：PCT/US2016/012788

    申请日：2016-01-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： KARDA, Kamal, M. ,  MILOJEVIC, Marko ,  WELLS, David, H. ,  GEALY, F., Daniel

    IPC: G11C11/21 ,  G11C11/34

    CPC classification number: H01L45/126 ,  G11C5/12 ,  G11C11/221 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/2418 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

    Abstract: An electronic device includes two conductive electrodes. A first current path extends from one of the electrodes to the other and has a dominant thermally activated conduction activation energy of 0.5 eV to 3.0 eV. A second current path extends from the one electrode to the other and is circuit-parallel the first current path. The second current path exhibits a minimum 100-times increase in electrical conductivity for increasing temperature within a temperature range of no more than 50°C between 300°C and 800°C and exhibits a minimum 100-times decrease in electrical conductivity for decreasing temperature within the 50°C temperature range. Other embodiments are disclosed.

    Abstract translation: 电子设备包括两个导电电极。 第一电流路径从一个电极延伸到另一个电极，并且具有0.5eV至3.0eV的显性热激活传导激活能。 第二电流路径从一个电极延伸到另一个电极并且与第一电流路径电路并联。 第二电流路径在300℃至800℃之间的不超过50℃的温度范围内提高温度的电导率最小为100倍，并且对于降低温度而言电导率降低至少100倍 在50°C的温度范围内。 公开了其他实施例。

    ELECTRICALLY ADDRESSABLE PASSIVE DEVICE, METHOD FOR ELECTRICAL ADDRESSING OF THE SAME AND USES OF THE DEVICE AND THE METHOD
    3.
    发明申请
    ELECTRICALLY ADDRESSABLE PASSIVE DEVICE, METHOD FOR ELECTRICAL ADDRESSING OF THE SAME AND USES OF THE DEVICE AND THE METHOD 审中-公开
    电寻址被动装置，电寻址方法及装置的使用方法和方法

    公开(公告)号：WO9858383A9

    公开(公告)日：1999-05-20

    申请号：PCT/NO9800185

    申请日：1998-06-17

    Applicant: OPTICOM AS ,  GUDESEN HANS GUDE ,  LEISTAD GEIRR I ,  NORDAL PER ERIK

    Inventor： GUDESEN HANS GUDE ,  LEISTAD GEIRR I ,  NORDAL PER-ERIK

    IPC: G11C11/42 ,  G11C11/21 ,  G11C13/00 ,  G11C13/02 ,  G11C13/04 ,  G11C16/02 ,  G11C17/00 ,  G11C17/14 ,  H03K19/12 ,  H03K19/14 ,  G11C11/22 ,  H03K19/177

    CPC classification number: G11C13/0014 ,  B82Y10/00 ,  G11C13/0016 ,  G11C13/04 ,  G11C17/00 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/77

    Abstract: An electrically addressable passive device for registration, storage and/or processing of data comprises a functional medium (1) in the form of a continuous or patterned structure (S) which may undergo a physical or chemical change of state. The functional medium (1) comprises individually addressable cells (2) which represent a registered or detected value or are assigned a predetermined logical value for the cell. The cell (2) is provided between the anode (3) and cathode (4) in an electrode means (E) which contacts the function medium in the cell and causes an electrical coupling therethrough, the functional medium having a non-linear impedance characteristic, whereby the cell (2) directly can be supplied with energy which effects a change in the state of the cell. In a method for electrical addressing of the passive device wherein the addressing comprises operations for i.a. detection and registration as well as further operations for writing, reading and switching of a logical value assigned to the cell, electric energy is applied directly to the functional medium of the cell in order to change its state and hence effect an addressing operation. Use in optical detector means, volumetric data storage devices or data processing devices.

    Abstract translation: 用于配准，存储和/或处理数据的电寻址无源器件包括呈可经历状态的物理或化学变化的连续或图案化结构（S）形式的功能介质（1）。 功能介质（1）包括单独可寻址的单元（2），其表示登记或检测到的值或者被分配给单元的预定逻辑值。 电池（2）设置在电极装置（E）中的阳极（3）和阴极（4）之间，该电极装置与电池中的功能介质接触并引起电耦合，功能介质具有非线性阻抗特性 由此电池（2）可以直接供应能够改变电池状态的能量。 在用于无源设备的电寻址的方法中，其中寻址包括用于i.a. 检测和登记以及用于写入，读取和切换分配给单元的逻辑值的进一步操作，将电能直接施加到单元的功能介质以便改变其状态并因此实现寻址操作。 用于光学检测装置，体积数据存储设备或数据处理设备。

    忆阻器存储芯片及其操作方法
    5.
    发明申请
    忆阻器存储芯片及其操作方法 审中-公开

    公开(公告)号：WO2021051551A1

    公开(公告)日：2021-03-25

    申请号：PCT/CN2019/117436

    申请日：2019-11-12

    Applicant: 华中科技大学

    Inventor： 王兴晟 ,  黄恩铭 ,  缪向水

    IPC: G11C11/21

    Abstract: 一种忆阻器芯片及其操作方法，包括电源管理模块（6），译码模块，存储模块（1），逻辑控制模块（4），读写模块（5），I/O模块（7）；读写模块（5）在选址后依据逻辑控制模块（4）提供的控制信号对存储阵列执行相应的操作，接口模块用于将读写模块（5）读出的数据输出，译码模块的行译码器（23）与存储模块（1）之间设置有字线电压转化模块（3），以此方式，输入至存储阵列中的字线晶体管栅极的电压是经过调节后的电压。按照该双极型忆阻器芯片及其操作方法，忆阻器存储器件限流后失效的可能性降低，器件高低阻分布会比较均匀，数据读出稳定并显著提高器件使用寿命，应用于多值忆阻器件，限流后阻态也会相应稳定。

    ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY
    6.
    发明申请
    ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY 审中-公开
    在一个交叉点阵列中并行存取记忆细胞

    公开(公告)号：WO2015038328A1

    公开(公告)日：2015-03-19

    申请号：PCT/US2014/052763

    申请日：2014-08-26

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： CASTRO, Hernan

    IPC: G11C11/21 ,  H01L27/115

    CPC classification number: G11C13/003 ,  G06F3/061 ,  G06F3/0658 ,  G06F3/0673 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0088 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77

    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.

    Abstract translation: 用于在交叉点阵列中并行访问存储器单元的方法和结构包括并行地访问设置在第一选定列和第一选定行之间的第一存储器单元和布置在与第一选定列不同的第二选定列之间的第二存储单元 列和与第一选定行不同的第二选定行。 并行访问包括同时在第一所选列和第一选定行之间以及在第二选定列与第二选定行之间应用访问偏移。 在小区处于阈值状态或小区处于阈值后恢复周期时，并行进行访问。

    SELF-HEATING BURN-IN
    7.
    发明申请
    SELF-HEATING BURN-IN 审中-公开
    自助烧

    公开(公告)号：WO2005019848A2

    公开(公告)日：2005-03-03

    申请号：PCT/US2004025439

    申请日：2004-08-06

    Applicant: INTEL CORP

    Inventor： NORRIS JEFFREY ,  SILVERIA RICHARD

    IPC: G01R31/316 ,  G11C11/21

    CPC classification number: G01R31/2875 ,  G01R31/2868 ,  G11C11/16 ,  G11C29/06

    Abstract: A method and an apparatus for self-heating burn-in have been disclosed. In one embodiment, a semiconductor device includes a plurality of gates, a multiplexer to select a clock signal out of a plurality of clock signals to toggle the plurality of gates in response to the selected clock signal to generate heat intenally for burn-in, and a thermal sensing circuitry to monitor an internal temperature.

    Abstract translation: 已经公开了一种用于自热老化的方法和装置。 在一个实施例中，半导体器件包括多个栅极，多路复用器，用于选择多个时钟信号中的时钟信号，以响应于所选择的时钟信号来切换多个门，以产生用于老化的热，以及 用于监测内部温度的热感测电路。

    EFFICIENT PLACEMENT OF MEMORY
    9.
    发明申请
    EFFICIENT PLACEMENT OF MEMORY 审中-公开

    公开(公告)号：WO2021076721A1

    公开(公告)日：2021-04-22

    申请号：PCT/US2020/055724

    申请日：2020-10-15

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： PARK, Jung Soo

    IPC: G06F13/38 ,  G11C11/21

    Abstract: An electronic apparatus includes a circuit board, a memory chip mounted on the circuit board, a memory controller to control an operation of the memory chip, a conductive pattern including a first control line to connect from a first terminal of the memory chip to a first terminal of the memory chip and a second control line to connect from a second terminal of the memory controller to a second terminal of the memory chip, and a capacitive element to provide a termination voltage. The first control line is connected to the capacitive element and the second control line is not connected to the capacitive element.

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