公开(公告)号：WO1998012706A1

公开(公告)日：1998-03-26

申请号：PCT/US1997014564

申请日：1997-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  FARNWORTH, Warren, M. ,  WARK, James, M. ,  NELSON, Eric, S. ,  DUESMAN, Kevin, G.

IPC: G11C29/00

CPC classification number: H01L22/22 ,  G01R31/2884 ,  G11C29/46 ,  G11C29/785 ,  G11C29/80 ,  G11C29/808 ,  H01L2224/48091 ,  H04J2203/0062 ,  H01L2924/00014

Abstract: An IC module (20), such as a Multi-Chip Module (MCM), includes multiple IC (12) dice each having a test mode enable bond pad (30), such as an output enable pad. A fuse incorporated into the MCM's substrate connects each dice's test mode enable pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable pads to one of the MCM's reference voltage pins. By applying a supply voltage to the test mode enable pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a reference voltage applied to the test mode enable pads through the reference voltage pins and the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging. A method for performing such testing once the test mode has been initiated and for repairing any failing elements found during testing, includes providing test signals to the dice, receiving response signals from the dice, evaluating the response signals to identify any failing elements in the dice, programming the failing elements addresses into anti-fuses in the dice with a programming voltage, confirming that the addresses are programmed by determining the resistance of the anti-fuses, re-testing the dice, receiving response signals from the re-tested dice, and evaluating the response signals to confirm all repairs.

Abstract translation: 诸如多芯片模块（MCM）的IC模块（20）包括多个具有测试模式使能接合焊盘（30）的IC（12）芯片，诸如输出使能焊盘。 集成到MCM基板中的保险丝将每个骰子的测试模式使能焊盘连接到MCM的无连接（N / C）引脚之一，并且连接到衬底中的电阻将测试模式使能焊盘连接到MCM的参考电压引脚之一 。 通过向测试模式使能焊盘通过N / C引脚施加电源电压，在骰子中启动测试模式。 一旦测试完成，保险丝可能会被熔断，并且施加到测试模式的参考电压使得焊盘能够通过参考电压引脚，并且电阻器将禁用骰子中的测试模式并启动操作模式。 因此，封装在IC模块中的裸片可以在封装后进行测试。 一旦测试模式已经启动并且用于修复在测试期间发现的任何故障元件，执行这种测试的方法包括向骰子提供测试信号，从骰子接收响应信号，评估响应信号以识别骰子中的任何故障元件 将故障元件地址编程为具有编程电压的骰子中的抗熔丝，通过确定抗熔丝的电阻，重新测试骰子，从重新测试的骰子接收响应信号来确认地址被编程， 并评估响应信号以确认所有维修。

公开(公告)号：WO1997025674A1

公开(公告)日：1997-07-17

申请号：PCT/US1996020113

申请日：1996-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  GILLIAM, Gary, R. ,  DUESMAN, Kevin, G. ,  NEVILL, Leland, R.

IPC: G06F11/20

CPC classification number: G11C29/80 ,  G11C29/808

Abstract: A memory device module in a package having externally accessible contacts includes multiple integrated memory circuits accessible to external circuitry exclusively through the contacts. An accessing circuit for each memory circuit accesses memory cells in the memory circuit for communication with the external circuitry. Each accessing circuit can be enabled to access redundant memory cells instead of inoperative memory cells by an enabling signal. An enabling circuit for each accessing circuit can output the enabling signal in response to receiving a unique set of input signals from external circuitry. Each unique set is selected with fuses in each enabling circuit, and includes row and column address strobe signals and a data signal. Upon receiving its unique set, one of the enabling circuits advantageously enables its associated accessing circuit to access redundant memory cells without the accessing circuits of the other memory circuits also being so enabled.

Abstract translation: 具有外部可访问触点的封装中的存储器件模块包括仅通过触点对外部电路可访问的多个集成存储器电路。 每个存储器电路的访问电路访问存储器电路中的存储器单元以与外部电路通信。 可以通过使能信号使每个访问电路能够访问冗余存储器单元而不是不工作的存储器单元。 每个访问电路的使能电路可以响应于从外部电路接收到一组唯一的输入信号而输出使能信号。 每个独特的集合在每个使能电路中选择熔丝，并包括行和列地址选通信号和数据信号。 在接收到其唯一的集合之后，启用电路之一有利地使其相关联的访问电路访问冗余存储器单元，而其他存储器电路的访问电路也被启用。

公开(公告)号：WO2020005543A1

公开(公告)日：2020-01-02

申请号：PCT/US2019/036696

申请日：2019-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： DUESMAN, Kevin, G. ,  DAVIS, James, E. ,  BOYER, Warren, L.

IPC: H01L25/07 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/60

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.

公开(公告)号：WO2019094120A1

公开(公告)日：2019-05-16

申请号：PCT/US2018/053862

申请日：2018-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： DAVIS, James, E. ,  DUESMAN, Kevin, G. ,  WRIGHT, Jeffrey, P. ,  BOYER, Warren, L.

IPC: H01L27/11524 ,  H01L23/00 ,  H01L23/528 ,  H01L27/02 ,  H01L25/065

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.

公开(公告)号：WO2019094097A1

公开(公告)日：2019-05-16

申请号：PCT/US2018/050072

申请日：2018-09-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： DAVIS, James, E. ,  PUSEY, John, B. ,  YIN, Zhiping ,  DUESMAN, Kevin, G.

IPC: H01L27/115 ,  H01L23/00 ,  H01L27/02

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

公开(公告)号：WO2003071549A1

公开(公告)日：2003-08-28

申请号：PCT/US2003/003674

申请日：2003-02-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CASPER, Stephen, L. ,  DUESMAN, Kevin, G. ,  HUSH, Glen

IPC: G11C11/34

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/79

Abstract: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

Abstract translation: 提供了用于读取可编程导体随机存取存储器PCRAM单元的电阻电平的感测电路。 通过从升高的行线电压激活存取晶体管，通过PCRAM单元引入电压电位差。 数字线和数位补码参考线都被预充电到第一预定电压。 被感测的电池具有通过PCRAM单元的可编程导体存储元件的电阻放电的预充电电压。 比较在数字线和参考导体读取的电压。 如果数字线上的电压大于参考电压，则将单元读为高电阻值，例如逻辑高电平，但如果在数字线上测量的电压低于参考电压，则读取单元 作为低电阻值，例如逻辑低电平。