公开(公告)号：WO2016025090A1

公开(公告)日：2016-02-18

申请号：PCT/US2015/037879

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： RANGARAJAN, Thanunathan ,  RISBUD, Vinayak P. ,  YASMIN, Tabassum

IPC: G06F1/20 ,  G06F12/00

CPC classification number: G06F1/206 ,  G06F11/3037 ,  G06F11/3058 ,  G11C5/04 ,  G11C7/04 ,  G11C29/20 ,  G11C29/46 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/0407 ,  G11C2029/0409 ,  Y02D10/16

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行指令的至少一个核和耦合到所述至少一个核的存储器控​​制器。 反过来，存储器控制器包括备用逻辑，用于响应于第一存储器件的温度超过热阈值，将存储在耦合到处理器的第一存储器件上的数据的动态传输耦合到耦合到处理器的第二存储器件 。 描述和要求保护其他实施例。

公开(公告)号：WO2015013023A3

公开(公告)日：2015-04-23

申请号：PCT/US2014045689

申请日：2014-07-08

Applicant: QUALCOMM INC

Inventor： KIM JUNG PILL ,  KIM TAEHYUN ,  KIM SUNGRYUL ,  KIM DAEIK D

IPC: G11C29/02

CPC classification number: G01R31/2851 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46

Abstract: A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.

Abstract translation: 电路包括响应于存储测试码的多个锁存器的多个晶体管。 电路还包括耦合到数据单元并耦合到读出放大器的第一位线。 电路还包括耦合到参考单元并耦合到读出放大器的第二位线。 来自一组多个晶体管的电流经由第一位线被施加到数据单元。 基于测试代码来确定多个晶体管的集合。 电路还包括耦合到第一位线和第二位线的测试模式参考电路。

公开(公告)号：WO02019339A1

公开(公告)日：2002-03-07

申请号：PCT/JP2001/007486

申请日：2001-08-30

IPC: G11C29/12 ,  G11C29/46 ,  G11C11/401 ,  G11C29/00

CPC classification number: G11C29/50016 ,  G11C11/401 ,  G11C29/12 ,  G11C29/46

Abstract: A semiconductor storage device in which an operation check can be made in the worst case of address combination and its testing method are disclosed. In testing the semiconductor storage device, specific data is written in a memory cell array (30), a test mode is set up by using a test signal (TE1) of 1 , a refresh address for test is stored in a data storage circuit (51), a first address for test is applied to an address terminal (21) thereby to conduct normal read or write according to the fist address, a second address for test is applied to the address terminal (21) thereby to conduct refresh according to the refresh address and to conduct normal read or write according to the second address, and data in the memory cell array (30) is checked to detect a false if any.

Abstract translation: 公开了一种半导体存储装置，其中可以在地址组合的最坏情况下进行操作检查及其测试方法。 在半导体存储装置的测试中，将特定数据写入存储单元阵列（30），通过使用测试信号（TE1）为1来建立测试模式，将用于测试的刷新地址存储在数据存储电路 51），将第一测试地址应用于地址终端（21），从而根据第一个地址进行正常的读取或写入，将第二测试地址应用于地址终端（21），从而根据 刷新地址并根据第二地址进行正常读取或写入，并且检查存储器单元阵列（30）中的数据以检测是否存在虚假（否）。

公开(公告)号：WO1997005622A1

公开(公告)日：1997-02-13

申请号：PCT/US1996011770

申请日：1996-07-17

Applicant: MICRON QUANTUM DEVICES, INC.

Inventor： MICRON QUANTUM DEVICES, INC. ,  ROOHPARVAR, Frankie, F. ,  RINERSON, Darrell, D. ,  CHEVALLIER, Christophe, J. ,  BRINER, Michael, S.

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C5/04 ,  G11C7/1045 ,  G11C16/04 ,  G11C16/20 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/46 ,  G11C2029/4402

Abstract: A memory system (10) capable of being configured for optimum performance after fabrication using control parameters stored in non-volatile data storage units (12A). The system includes an array of memory cells (12) separate from the data storage units (12A), arranged in a multiplicity of rows and columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line. Control circuitry (19) for controlling memory operations such as programming the memory cells and reading the memory cells when the memory system is in a normal mode of operation. The non-volatile data storage units (12A) store control parameter data used by the control means for controlling the memory operations, with the control parameters being modifiable when the memory system is placed in an alternative mode of operation as opposed the normal mode of operation. Once the memory has been fabricated and characterized, the control parameters can be selected for optimum memory performance and loaded into the data storage units.

Abstract translation: 一种存储系统（10），其能够被配置为在使用存储在非易失性数据存储单元（12A）中的控制参数进行制造之后的最佳性能。 该系统包括与数据存储单元（12A）分离的存储单元（12）的阵列，排列成多个行和列，每个单元位于一行中，其中一个行耦合到公共字线，并且与每个单元 位于一列中的一个被耦合到公共位线。 用于控制存储器操作的控制电路（19），例如当存储器系统处于正常操作模式时对存储器单元进行编程和读取存储器单元。 非挥发性数据存储单元（12A）存储由控制装置使用的用于控制存储器操作的控制参数数据，当存储器系统处于替代操作模式时，控制参数是可修改的，而不是正常操作模式 。 一旦存储器被制造和表征，可以选择控制参数以获得最佳的存储器性能并加载到数据存储单元中。

公开(公告)号：WO2017131700A1

公开(公告)日：2017-08-03

申请号：PCT/US2016/015373

申请日：2016-01-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： POPE, Eric L.

IPC: G11C29/44 ,  G11C29/52

CPC classification number: G11C29/44 ,  G11C29/46 ,  G11C29/52 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: Addresses of memory cells that have errors corrected by error correction operations are evaluated to identify a failed row of memory. A post package repair is implemented on the failed row with a method comprising obtaining indications of the error correction operations, logging addresses of memory cells having errors corrected by the error correction operations, evaluating the addresses to identify the failed row, and implementing the post package repair operation on the failed row.

Abstract translation: 评估通过纠错操作纠正了错误的存储器单元的地址以识别存储器的失败行。 利用包括获得错误校正操作的指示，记录具有由纠错操作校正的错误的存储器单元的地址，评估地址以识别失败的行以及实现后置封装的方法来在失败的行上实施后封装修复 修复失败的行上的操作。

公开(公告)号：WO2016077248A1

公开(公告)日：2016-05-19

申请号：PCT/US2015/059786

申请日：2015-11-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WILSON, Alan, J. ,  WRIGHT, Jeffrey, P.

IPC: G11C5/04 ,  G11C5/06

CPC classification number: G11C7/20 ,  G11C5/063 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/06 ,  G11C16/20 ,  G11C17/18 ,  G11C29/021 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/14 ,  G11C29/46 ,  G11C29/70

Abstract: Memory die can be stacked to form a three-dimensional integrated circuit. For example, through-silicon vias (TSVs) can permit signals to pass vertically through the three-dimensional integrated circuit. Disclosed herein are apparatuses and methods to perform post package trimming of memory die, which advantageously permits the memory die to be trimmed after the memory die is stacked, such that test and trimming characteristics are relatively close to that which will be actually be encountered.

Abstract translation: 存储芯片可堆叠形成三维集成电路。 例如，硅通孔（TSV）可以允许信号垂直穿过三维集成电路。 这里公开了用于执行存储管芯的后封装修整的装置和方法，其有利地允许在存储器管芯堆叠之后对存储管芯进行修整，使得测试和修整特性相对接近将实际遇到的特性。

公开(公告)号：WO2015153649A1

公开(公告)日：2015-10-08

申请号：PCT/US2015/023651

申请日：2015-03-31

Applicant: INTEL CORPORATION

Inventor： MOZAK, Christopher, P. ,  BAINS, Kuljit, S.

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/068 ,  G06F11/2094 ,  G06F2201/805 ,  G11C7/1045 ,  G11C7/24 ,  G11C29/025 ,  G11C29/46 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/76 ,  G11C29/83

Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

Abstract translation: 在一个实施例中，存储器设备可以包含设备处理逻辑和模式寄存器。 模式寄存器可以是可以指定存储器件的操作模式的寄存器。 模式寄存器中的字段可以保存可以指示与存储器设备相关联的命令是否被禁用的值。 该值可以保持在现场，直到存储器件被上电或复位为止。 设备处理逻辑可以获取命令的实例。 设备处理逻辑可以基于模式寄存器保持的值来确定该命令是否被禁用。 如果设备处理逻辑确定该命令被禁用，则设备处理逻辑可能不执行该命令的实例。 如果设备处理逻辑确定命令未被禁止，则设备处理逻辑可以执行该命令的实例。

公开(公告)号：WO9847060A2

公开(公告)日：1998-10-22

申请号：PCT/US9806665

申请日：1998-04-03

Applicant: DALLAS SEMICONDUCTOR

Inventor： LITTLE WENDELL L ,  CURRY STEPHEN M ,  LOOMIS DONALD W ,  SCHLUNDT CONRAD F

IPC: G06F12/14 ,  G06F21/00 ,  G11C29/46 ,  G06F1/00

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F21/554 ,  G06F2207/7219 ,  G11C29/46

Abstract: A microcontroller communicating via a data path and an address path with a memory block containing encrypted contents, the microcontroller including the capability for detecting resets effectuated in the wake of an unauthorized attempt to gain access to the encrypted contents and the capability of evading such an unauthorized attempt.

Abstract translation: 通过数据路径和地址路径与包含加密内容的存储块进行通信的微控制器，微控制器包括在未经授权的尝试访问加密内容之后实现的检测复位的能力，以及逃避这种未经授权的能力 尝试。

公开(公告)号：WO1998018134A1

公开(公告)日：1998-04-30

申请号：PCT/US1997018734

申请日：1997-10-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SHER, Joseph, C. ,  MERRITT, Todd, A.

IPC: G11C29/00

CPC classification number: G01R31/31701 ,  G11C29/46

Abstract: A supervoltage circuit has been described which uses a resistor divider as an input stage. The resistor divider decreases the dependency of the supervoltage trip point on transistor threshold voltages (Vt). The stability of supervoltage trip point is significantly increased over traditional supervoltage circuits using diode connected transistors as an input stage. The supervoltage circuit can be included in any integrated circuit including memory devices.

Abstract translation: 已经描述了使用电阻分压器作为输入级的超压电路。 电阻分压器降低了超级电压跳变点对晶体管阈值电压（Vt）的依赖性。 与使用二极管连接的晶体管作为输入级的传统超压电路相比，超级电压跳变点的稳定性显着提高。 超级电路可以包括在包括存储器件的任何集成电路中。

公开(公告)号：WO2006091468A2

公开(公告)日：2006-08-31

申请号：PCT/US2006/005462

申请日：2006-02-16

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  MASGRAS, Cristian, P. ,  PYSKA, Michael ,  BOLES, Edawrd, Brian ,  TRIECE, Joseph, W. ,  WOJEWODA, Igor ,  CHEN, Mei-Ling

Inventor： MASGRAS, Cristian, P. ,  PYSKA, Michael ,  BOLES, Edawrd, Brian ,  TRIECE, Joseph, W. ,  WOJEWODA, Igor ,  CHEN, Mei-Ling

CPC classification number: G01R31/31701 ,  G06F11/273 ,  G11C29/003 ,  G11C29/46

Abstract: A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.

Abstract translation: 特殊模式键匹配比较模块具有N存储元件和特殊模式键匹配比较器。 N存储元件累积串行数据流，然后确定数字设备是否应该以普通用户模式，公共编程模式或特定专用测试模式中操作。 为了减少意外解码错误测试或编程模式的可能性，数据流具有足够大数量的N位，从而大大降低了伪解码的可能性。 为了进一步降低意外解码编程或测试模式的可能性，如果在N位串行数据流的累积期间检测到少于或多于N个时钟，则特殊模式密钥匹配比较模块可以被复位。 特殊模式键匹配数据模式可以表示正常的用户模式，公共编程模式和特定的私人制造商测试模式。