公开(公告)号：WO2020068354A1

公开(公告)日：2020-04-02

申请号：PCT/US2019/048820

申请日：2019-08-29

申请人： MICRON TECHNOLOGY, INC.

发明人： ROSS, Frank F.

IPC分类号： G11C8/16 ,  G11C7/10

摘要： The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.

公开(公告)号：WO2021133826A1

公开(公告)日：2021-07-01

申请号：PCT/US2020/066664

申请日：2020-12-22

申请人： MICRON TECHNOLOGY, INC.

发明人： KEETH, Brent ,  ROSS, Frank F. ,  MURPHY, Richard C.

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G11C11/54 ,  G06F13/1668 ,  G06N3/004 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18

摘要： Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.

公开(公告)号：WO2018102336A1

公开(公告)日：2018-06-07

申请号：PCT/US2017/063581

申请日：2017-11-29

申请人： MICRON TECHNOLOGY, INC.

发明人： WALKER, Robert M. ,  ROSS, Frank F.

IPC分类号： G06F13/16

摘要： The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

公开(公告)号：WO2020180574A1

公开(公告)日：2020-09-10

申请号：PCT/US2020/020008

申请日：2020-02-27

申请人： MICRON TECHNOLOGY, INC.

发明人： ROSS, Frank F. ,  PRATHER, Matthew A.

IPC分类号： G06F13/16 ,  G11C7/22

摘要： The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

公开(公告)号：WO2020180440A1

公开(公告)日：2020-09-10

申请号：PCT/US2020/016485

申请日：2020-02-04

申请人： MICRON TECHNOLOGY, INC.

发明人： ROSS, Frank F. ,  PRATHER, Matthew A.

IPC分类号： G06F12/06 ,  G06F13/16 ,  G06F3/06 ,  G11C5/04

摘要： Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

公开(公告)号：WO2020068363A1

公开(公告)日：2020-04-02

申请号：PCT/US2019/049001

申请日：2019-08-30

申请人： MICRON TECHNOLOGY, INC.

发明人： ROSS, Frank F.

IPC分类号： G06F3/06

摘要： The present disclosure includes apparatuses and methods related to a memory apparatus and/or method for addressing in memory with a read identification (RID) number. An example apparatus can include a first memory device, a second memory device coupled to the first memory device, and a controller coupled to the first memory device and the second memory device, wherein the controller is configured to receive a read command requesting data from the first memory device, wherein the read command includes a read identification (RID) number that includes an address to identify a location of the data in the first memory device, and transfer the data from the location in the first memory device to the second memory device in response receiving the read command.

公开(公告)号：WO2018190947A1

公开(公告)日：2018-10-18

申请号：PCT/US2018/018106

申请日：2018-02-14

申请人： MICRON TECHNOLOGY, INC.

发明人： ROSS, Frank F. ,  WALKER, Robert M.

IPC分类号： G06F13/16

摘要： The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.

公开(公告)号：WO2017192346A1

公开(公告)日：2017-11-09

申请号：PCT/US2017/029780

申请日：2017-04-27

申请人： MICRON TECHNOLOGY, INC.

发明人： WALKER, Robert M. ,  HALL, JR., James A. ,  ROSS, Frank F.

IPC分类号： G06F13/16

摘要： The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

摘要翻译： 本公开包括涉及非确定性存储器协议的装置和方法。 示例装置可以基于根据协议从主机接收的命令在存储器设备上执行操作，其中协议包括操作的非确定性定时。 存储设备可以是非易失性双列直插式内存模块（NVDIMM）设备。