公开(公告)号：WO2012036728A2

公开(公告)日：2012-03-22

申请号：PCT/US2011001573

申请日：2011-09-13

Applicant: MICRON TECHNOLOGY INC ,  KRAMER STEPHEN J ,  SANDHU GURTEJ S

Inventor： KRAMER STEPHEN J ,  SANDHU GURTEJ S

IPC: G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08

Abstract: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material and a multiferroic material in contact with the ferromagnetic storage material, wherein the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are located between a first electrode and a second electrode.

Abstract translation: 自旋转矩传输（STT）存储器单元结构和方法在本文中描述。 一个或多个STT存储器单元结构包括位于铁磁存储材料和与反铁磁材料接触的钉扎铁磁材料和与铁磁存储材料接触的多铁性材料之间的钉扎铁磁材料之间的隧穿势垒材料，其中反铁磁材料，铁磁存储材料 并且钉扎铁磁材料位于第一电极和第二电极之间。

公开(公告)号：WO2010059451A3

公开(公告)日：2010-08-26

申请号：PCT/US2009063761

申请日：2009-11-09

Applicant: MICRON TECHNOLOGY INC ,  SRINIVASAN BHASKAR ,  SANDHU GURTEJ S

Inventor： SRINIVASAN BHASKAR ,  SANDHU GURTEJ S

IPC: H01L29/861

CPC classification number: H01L29/88 ,  H01L21/3205 ,  H01L27/1021 ,  Y10S438/957

Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select device may comprise, for example, a metal insulator insulator metal (MIIM) device. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.

Abstract translation: 公开了包括用作具有低介电常数的高带隙材料的开放体积的器件。 开放体积可以在选择器件中提供更加非线性的非对称I-V曲线和增强的整流行为。 选择装置可以包括例如金属绝缘体绝缘金属（MIIM）装置。 可以使用各种方法来形成包括这种选择装置的选择装置和存储器系统。 存储器设备和电子系统包括这种选择设备。

公开(公告)号：WO2007127496A8

公开(公告)日：2010-08-19

申请号：PCT/US2007011524

申请日：2007-05-14

Applicant: MICRON TECHNOLOGY INC ,  SANDHU GURTEJ S

Inventor： SANDHU GURTEJ S

IPC: B82B3/00 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/3081 ,  G03F7/0002 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  Y10T428/24058 ,  Y10T428/2995

Abstract: A pattern having exceptionally small features is formed on a partially fabricated integrated circuit (102) during integrated circuit fabrication. The pattern comprises features (162), (164) formed by self-organizing material, such as diblock copolymers. The organization of the copolymers is directed by spacers (152) which have been formed by a pitch multiplication process in which the spacers (152) are formed at the sides of sacrificial mandrels (142), which are later removed to leave the spaced-apart, free-standing spacers (152). Diblock copolymers, composed of two immiscible block species, are deposited over and in the space between the spacers (152). The copolymers are made to self-organize, with each block species aggregating with other block species of the same type.

Abstract translation: 在集成电路制造期间，在部分制造的集成电路（102）上形成具有特别小特征的图案。 图案包括由自组织材料形成的特征（162），（164），例如二嵌段共聚物。 共聚物的组织由间隔物（152）引导，间隔物（152）已经通过间距倍增过程形成，其中间隔物（152）形成在牺牲心轴（142）的侧面，后者被去除以离开间隔开 ，独立式间隔件（152）。 由两个不混溶的嵌段物质组成的二嵌段共聚物沉积在间隔物（152）之上和之间的空间中。 使共聚物自组织，每个嵌段物质与相同类型的其它嵌段物种聚集。

公开(公告)号：WO2010065252A3

公开(公告)日：2010-08-12

申请号：PCT/US2009064004

申请日：2009-11-11

Applicant: MICRON TECHNOLOGY INC ,  SILLS SCOTT ,  SANDHU GURTEJ S ,  DEVILLIERS ANTON

Inventor： SILLS SCOTT ,  SANDHU GURTEJ S ,  DEVILLIERS ANTON

IPC: H01L21/027 ,  H01L21/20 ,  H01L21/302

CPC classification number: H01L21/3088 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/31138

Abstract: A method of fabricating a substrate includes forming spaced first features over a substrate. An alterable material is deposited over the spaced first features and the alterable material is altered with material from the spaced first features to form altered material on sidewalls of the spaced first features. A first material is deposited over the altered material, and is of some different composition from that of the altered material. The first material is etched to expose the altered material and spaced second features comprising the first material are formed on sidewalls of the altered material. Then, the altered material is etched from between the spaced second features and the spaced first features. The substrate is processed through a mask pattern comprising the spaced first features and the spaced second features. Other embodiments are disclosed.

Abstract translation: 一种制造衬底的方法包括在衬底上形成间隔开的第一特征。 可变材料沉积在间隔开的第一特征上，并且可变材料用来自间隔开的第一特征的材料改变以在间隔开的第一特征的侧壁上形成改变的材料。 第一种材料沉积在改变的材料上，并且与改变的材料的组成不同。 蚀刻第一材料以暴露改变的材料，并且包含第一材料的间隔开的第二特征形成在改变的材料的侧壁上。 然后，从间隔开的第二特征和间隔开的第一特征之间蚀刻改变的材料。 通过包括间隔开的第一特征和间隔开的第二特征的掩模图案来处理衬底。 公开了其它实施例。

公开(公告)号：WO2009154886A3

公开(公告)日：2010-02-18

申请号：PCT/US2009042540

申请日：2009-05-01

Applicant: MICRON TECHNOLOGY INC ,  SANDHU GURTEJ S ,  SRINIVASAN BHASKAR

Inventor： SANDHU GURTEJ S ,  SRINIVASAN BHASKAR

IPC: H01L29/861

CPC classification number: H01L45/00 ,  Y10S257/91 ,  Y10S438/90 ,  Y10S438/902 ,  Y10S438/983

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract translation: 一些实施例包括形成二极管的方法。 所述方法可以包括氧化导电电极的上表面以在导电电极上形成氧化物层。 在一些实施方案中，所述方法可包括在导电电​​极上形成可氧化材料，以及随后氧化可氧化材料以在导电电极上形成氧化物层。 在一些实施例中，所述方法可包括在导电电​​极上形成金属卤化物层。 一些实施例包括在一对二极管电极之间包含金属卤化物层的二极管。

公开(公告)号：WO2008045202A3

公开(公告)日：2009-03-05

申请号：PCT/US2007020687

申请日：2007-09-25

Applicant: MICRON TECHNOLOGY INC ,  SMYTHE JOHN A ,  SANDHU GURTEJ S ,  COPPA BRIAN J ,  SURTHI SHYAM ,  MENG SHUANG

Inventor： SMYTHE JOHN A ,  SANDHU GURTEJ S ,  COPPA BRIAN J ,  SURTHI SHYAM ,  MENG SHUANG

IPC: H01L21/314 ,  H01L21/033 ,  H01L21/308 ,  H01L21/316

CPC classification number: H01L21/3088 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3141 ,  H01L21/31612

Abstract: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.

Abstract translation: 公开了通过间距倍增来控制半导体制造期间尺寸减小的特征的关键尺寸的方法。 间距倍增通过通过常规光致抗蚀剂技术图案化掩模结构并随后将图案转移到牺牲材料来实现。 然后通过原子层沉积沉积保形材料之后，在转印图案的垂直表面上形成间隔区。 然后将间隔区域以及因此减小的特征转移到半导体衬底。

公开(公告)号：WO2008019039A3

公开(公告)日：2008-09-12

申请号：PCT/US2007017297

申请日：2007-08-02

Applicant: MICRON TECHNOLOGY INC ,  PRALL KIRK D ,  SANDHU GURTEJ S

Inventor： PRALL KIRK D ,  SANDHU GURTEJ S

IPC: H01L21/28 ,  H01L29/423

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L29/42332

Abstract: A method of fabricating a memory cell including forming nanodots (106) over a first dielectric layer (104) and forming an intergate dielectric layer (110) over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer (120) is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer. The spacing layer can fill hollows or voids (119) where a nanodot has been removed at the sidewall, thereby preventing the loss of data retention in the cell.

Abstract translation: 一种制造存储单元的方法，包括在第一介电层（104）上形成纳米点（106），并在纳米点上形成隔间介电层（110），其中隔间电介质层封装在纳米点上。 为了形成存储器单元的侧壁，隔离介电层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 间隔层（120）形成在侧壁上以覆盖其中已经沉积纳米点的位置，并且间隙电介质层和纳米点的剩余部分可以用对栅极间介电层的选择性蚀刻去除。 间隔层可以填充中空或空隙（119），其中已经在侧壁处去除了纳米点，从而防止了电池中数据保留的损失。

公开(公告)号：WO2008008157A3

公开(公告)日：2008-05-29

申请号：PCT/US2007014446

申请日：2007-06-21

Applicant: MICRON TECHNOLOGY INC ,  WILLIAMSON MARK J ,  JOHNSON PAUL M ,  LYONSMITH SHAWN D ,  SANDHU GURTEJ S ,  ARRINGTON JUSTIN R

Inventor： WILLIAMSON MARK J ,  JOHNSON PAUL M ,  LYONSMITH SHAWN D ,  SANDHU GURTEJ S ,  ARRINGTON JUSTIN R

IPC: H01L21/66

CPC classification number: G01N1/32

Abstract: A method of imaging and identifying defects and contamination on the surface of an integrated circuit is described. The method may be used on areas smaller than one micron in diameter. An energetic beam, such as an electron beam, is directed at a selected IC location having a layer of a solid, fluid or gaseous reactive material formed over the surface. The energetic beam disassociates the reactive material in the region into chemical radicals that either chemically etch the surface preferentially, or deposit a thin layer of a conductive material over the local area around the energetic beam. The surface may be examined as various layers are selectively etched to decorate defects and/or as various layers are locally deposited in the area around the energetic beam. SEM imaging and other analytic methods may be used to identify the problem more easily.

Abstract translation: 描述了成像和识别集成电路表面上的缺陷和污染的方法。 该方法可用于直径小于1微米的区域。 诸如电子束的高能束被引导至具有在表面上形成的固体，流体或气体反应材料层的选定IC位置。 高能束将该区域中的反应性材料分解成化学基团，化学基团优先化学蚀刻表面，或者在高能束周围的局部区域上沉积薄层导电材料。 当各种层被选择性地蚀刻以修饰缺陷和/或当各层在局部沉积在高能束周围的区域时可检查表面。 可以使用SEM成像和其他分析方法来更容易地识别问题。

公开(公告)号：WO2004102592B1

公开(公告)日：2005-03-10

申请号：PCT/US2004013963

申请日：2004-05-04

Applicant: MICRON TECHNOLOGY INC

Inventor： BASCERI CEM ,  GEALY F DANIEL ,  SANDHU GURTEJ S

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/334

CPC classification number: H01L27/10855 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/57

Abstract: The invention includes methods in which metal oxide dielectric materials (50) are deposited over barrier layers (48). The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The dielectric material/barrier layer constructions can be incorporated into capacitors. The capacitors can be used in, for example, DRAM cells, which in turn can be used in electronic systems.

Abstract translation: 本发明包括其中金属氧化物介电材料（50）沉积在阻挡层（48）上的方法。 阻挡层可以包括金属和碳，硼和氮中的一种或多种的组合物，并且介电材料的金属氧化物可以包含与阻挡层相同的金属。 电介质材料/阻挡层结构可以结合到电容器中。 电容器可以用在例如DRAM单元中，DRAM单元又可以用在电子系统中。

公开(公告)号：WO0117004A3

公开(公告)日：2002-03-21

申请号：PCT/US0024173

申请日：2000-09-01

Applicant: MICRON TECHNOLOGY INC

Inventor： SHARAN SUJIT ,  SANDHU GURTEJ S ,  GILTON TERRY L

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  C23C16/02 ,  H01L21/306

CPC classification number: H01L21/76877 ,  H01L21/28518 ,  Y10S438/906

Abstract: The invention includes methods of forming a conductive silicide layers on silicon comprising substrates, and methods of forming conductive silicide contacts. In one implementation, a method of forming a conductive silicide layer on a silicon comprising substrate includes reacting oxygen with silicon of a silicon comprising substrate to form oxides of silicon from silicon of the substrate. The oxides of silicon include stoichiometric silicon dioxide and substoichiometric silicon dioxide. The stoichiometric silicon dioxide and substoichiometric silicon dioxide are exposed to ozone to transform at least some of the substoichiometric silicon dioxide to stoichiometric silicon dioxide. After the exposing, a conductive metal silicide is formed in electrical connection with silicon of the silicon comprising substrate. In one implementation, a method of forming a conductive silicide layer on a silicon comprising substrate includes reacting oxygen with silicon of a silicon comprising substrate to form oxides of silicon from silicon of the substrate. The oxides of silicon include stoichiometric silicon dioxide and substoichiometric silicon dioxide. The stoichiometric silicon dioxide and substoichiometric silicon dioxide are exposed to O2 plasma to transform at least some of the substoichiometric silicon dioxide to stoichiometric silicon dioxide. After the exposing, a metal is reacted with silicon of the substrate to form a conductive metal silicide.

Abstract translation: 本发明包括在含硅衬底上形成导电硅化物层的方法，以及形成导电硅化物接触的方法。 在一个实施方案中，在包含硅的衬底上形成导电硅化物层的方法包括使氧与含硅衬底的硅反应以从衬底​​的硅形成硅的氧化物。 硅的氧化物包括化学计量的二氧化硅和亚化学计量的二氧化硅。 将化学计量的二氧化硅和亚化学计量的二氧化硅暴露于臭氧以将至少一些亚化学计量的二氧化硅转化为化学计量的二氧化硅。 暴露后，形成导电金属硅化物与含硅衬底的硅电连接。 在一个实施方案中，在包含硅的衬底上形成导电硅化物层的方法包括使氧与含硅衬底的硅反应以从衬底​​的硅形成硅的氧化物。 硅的氧化物包括化学计量的二氧化硅和亚化学计量的二氧化硅。 将化学计量的二氧化硅和亚化学计量的二氧化硅暴露于O 2等离子体中以将至少一些亚化学计量的二氧化硅转化为化学计量的二氧化硅。 暴露后，金属与基板的硅反应形成导电金属硅化物。