公开(公告)号：WO2009148863A3

公开(公告)日：2010-02-25

申请号：PCT/US2009045059

申请日：2009-05-22

Applicant: MICRON TECHNOLOGY INC ,  LABERGE PAUL A ,  JOHNSON JAMES B

Inventor： LABERGE PAUL A ,  JOHNSON JAMES B

IPC: G11C11/409 ,  G11C7/22

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0629 ,  G06F3/0673 ,  G06F3/0689 ,  G06F5/06 ,  G06F13/1689 ,  G06F2003/0697 ,  G11C7/1051 ,  G11C7/222 ,  Y02D10/14

Abstract: Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.

Abstract translation: 本发明的实施例提供了具有共享用于传输读取数据的接口的多个存储器件的存储器系统。 控制器可以识别发送到不同存储器件的连续读取请求。 为了避免接口上的数据争用，例如，控制器可被配置为延迟时间，直到对应于第二读请求的读取数据被放置在接口上。

公开(公告)号：WO2010011503A3

公开(公告)日：2010-04-15

申请号：PCT/US2009050155

申请日：2009-07-09

Applicant: MICRON TECHNOLOGY INC ,  LABERGE PAUL A ,  JEDDELOH JOSEPH M ,  JOHNSON JAMES B

Inventor： LABERGE PAUL A ,  JEDDELOH JOSEPH M ,  JOHNSON JAMES B

IPC: G11C5/02 ,  G11C7/00 ,  G11C7/22 ,  H01L23/12

CPC classification number: G11C7/1072 ,  G06F12/00 ,  G11C5/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/107

Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

Abstract translation: 存储器系统和方法使用彼此耦合并且耦合到逻辑裸片的堆叠存储器器件管芯。 逻辑裸片可以包括定时校正系统，该定时校正系统可操作以控制逻辑裸片接收来自每个存储器件裸片的信号（诸如读取数据信号）的时序。 定时校正通过调整施加到每个存储设备骰子的各个选通信号（例如读选通信号）的定时来控制读数据或其他信号的定时。 存储设备管芯可以在由接收相应选通信号的时间确定的时间将读取数据传输到存储器设备。 每个选通信号的定时被调整，使得来自所有存储器装置骰子的读取数据或其他信号同时被接收。

公开(公告)号：WO2006121874A3

公开(公告)日：2007-08-02

申请号：PCT/US2006017439

申请日：2006-05-04

Applicant: MICRON TECHNOLOGY INC ,  JOHNSON JAMES B ,  MANNING TROY A

Inventor： JOHNSON JAMES B ,  MANNING TROY A

IPC: G01R31/26

CPC classification number: G11C7/1039 ,  G11C7/1048 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/105 ,  G11C2207/2254

Abstract: A synchronous dynamic random access memory ("SDRAM") device (100) includes a pipelined write data path coupling data from a data bus to a DRAM array (122), and a pipelined read data path coupling read data from the array ((122) to the data bus. The SDRAM device also includes a bypass path allowing the write data in the write data path to be coupled directly to the read data path without firs being stored in the DRAM array. The write data are preferably coupled through the write data path by issuing a write command to the DRAM device, and the read data are preferably coupled through the read data path by issuing a read command to the DRAM device. The memory array is inhibited from responding to these commands so that the write data are not stored in the array, and read data from the array are not coupled to the read data path.

Abstract translation: 同步动态随机存取存储器（“SDRAM”）装置（100）包括将从数据总线到DRAM阵列（122）的数据耦合的流水线写入数据路径，以及将读取数据从阵列（（122 ）SDRAM装置还包括旁路路径，允许写入数据路径中的写入数据直接耦合到读取数据路径，而没有保存在DRAM阵列中的数据，写入数据优选地通过写入 通过向DRAM设备发出写入命令，读取数据优选地通过读取数据路径耦合到DRAM设备，读取命令被禁止响应于这些命令，使得写入数据是 不存储在阵列中，并且从阵列读取数据不会耦合到读取的数据路径。