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    DYNAMIC COMMAND AND/OR ADDRESS MIRRORING SYSTEM AND METHOD FOR MEMORY MODULES
    6.
    发明申请
    DYNAMIC COMMAND AND/OR ADDRESS MIRRORING SYSTEM AND METHOD FOR MEMORY MODULES 审中-公开
    用于存储器模块的动态命令和/或地址映射系统和方法

    公开(公告)号：WO2005076823A3

    公开(公告)日：2006-07-06

    申请号：PCT/US2005002553

    申请日：2005-01-26

    Applicant: MICRON TECHNOLOGY INC ,  LABERGE PAUL A

    Inventor： LABERGE PAUL A

    IPC: G06F12/00 ,  G06F12/06 ,  G11C5/00

    CPC classification number: G11C5/00 ,  G06F12/0653

    Abstract: A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite surfaces being interconnected. A memory hub mounted on each module alters the configuration of address and/or command signals coupled to the memory devices depending upon whether the memory devices on the first surface of the substrate or the memory devices on the second surface of the substrate are being accessed. Alternatively, the configuration of the address and/or command signals coupled to mirrored memory devices may be altered by a register mounted on the substrate that is coupled to the memory devices or by a memory controller coupled directly to memory devices on one or more memory modules.

    Abstract translation: 存储器模块包括将信号耦合到安装在存储器模块基板的相对的第一和第二表面上的存储器件的存储器集线器。 存储器件安装在镜像配置中，其相对表面上的存储器件的镜像端子被互连。 安装在每个模块上的存储器毂根据衬底的第一表面上的存储器件或衬底的第二表面上的存储器件是否被访问来改变耦合到存储器件的地址和/或命令信号的配置。 或者，耦合到镜像存储器设备的地址和/或命令信号的配置可以由安装在衬底上的寄存器改变，该寄存器耦合到存储器件，或者由直接耦合到一个或多个存储器模块上的存储器件的存储器控​​制器 。

    DELAY LINE SYNCHRONIZER APPARATUS AND METHOD
    8.
    发明申请
    DELAY LINE SYNCHRONIZER APPARATUS AND METHOD 审中-公开
    延时线同步装置和方法

    公开(公告)号：WO2005101164A2

    公开(公告)日：2005-10-27

    申请号：PCT/US2005/009404

    申请日：2005-03-18

    Applicant: MICRON TECHNOLOGY, INC. ,  LABERGE, Paul, A.

    Inventor： LABERGE, Paul, A.

    IPC: G06F1/04

    CPC classification number: G06F1/12

    Abstract: A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.

    Abstract translation: 同步器系统和方法可以与传统的可调节延迟电路一起使用，以便在输出时钟信号之一的可调节延迟电路的时间延迟被改变时，保持不同时钟域的时钟信号之间的伪同步相位关系 。

    MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE
    9.
    发明申请
    MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE 审中-公开
    多串行接口堆叠存储器架构

    公开(公告)号：WO2010051461A1

    公开(公告)日：2010-05-06

    申请号：PCT/US2009/062799

    申请日：2009-10-30

    Applicant: MICRON TECHNOLOGY, INC. ,  JEDDELOH, Joe M. ,  LABERGE, Paul A.

    Inventor： JEDDELOH, Joe M. ,  LABERGE, Paul A.

    IPC: G06F12/14 ,  G06F12/16

    CPC classification number: G06F13/1668 ,  G06F13/1684 ,  G06F13/4022 ,  G06F2213/16 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.

    Abstract translation: 本文公开的系统和方法基本上同时传送跨越一个或多个发起设备或诸如处理器和交换机的目的地设备之间的对应多个串行化通信链路接口（SCLI）的多个命令，地址和/或数据流。 在交换机上，可以将与每个流相对应的一个或多个命令，地址或数据传送到与对应的存储器保险库相关联的对应的目的地存储器保管库控制器（MVC）。 目的地MVC可以独立于与耦合到对应的多个存储器库的其他MVC相关联的并行操作执行写入操作，读取操作和/或存储器保管库内务处理操作。

    MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM
    10.
    发明申请
    MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM 审中-公开
    存储器系统和使用堆叠的存储器器件的方法，以及使用存储器系统的系统

    公开(公告)号：WO2010011503A3

    公开(公告)日：2010-04-15

    申请号：PCT/US2009050155

    申请日：2009-07-09

    Applicant: MICRON TECHNOLOGY INC ,  LABERGE PAUL A ,  JEDDELOH JOSEPH M ,  JOHNSON JAMES B

    Inventor： LABERGE PAUL A ,  JEDDELOH JOSEPH M ,  JOHNSON JAMES B

    IPC: G11C5/02 ,  G11C7/00 ,  G11C7/22 ,  H01L23/12

    CPC classification number: G11C7/1072 ,  G06F12/00 ,  G11C5/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/107

    Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

    Abstract translation: 存储器系统和方法使用彼此耦合并且耦合到逻辑裸片的堆叠存储器器件管芯。 逻辑裸片可以包括定时校正系统，该定时校正系统可操作以控制逻辑裸片接收来自每个存储器件裸片的信号（诸如读取数据信号）的时序。 定时校正通过调整施加到每个存储设备骰子的各个选通信号（例如读选通信号）的定时来控制读数据或其他信号的定时。 存储设备管芯可以在由接收相应选通信号的时间确定的时间将读取数据传输到存储器设备。 每个选通信号的定时被调整，使得来自所有存储器装置骰子的读取数据或其他信号同时被接收。

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