Abstract:
Certain computer systems having centralized power sources are described herein. In one embodiment, a computer system can include a processing unit and an enclosure containing the processing unit. The processing unit includes a motherboard having a processor and a clock circuitry operatively coupled to the processor. The processing unit can also include a power supply that includes a first rail configured to supply power at a first voltage to the processor on the motherboard and a second rail configured to supply power at a second voltage to the clock circuitry on the motherboard. The motherboard does not include a coin-type battery electrically coupled to the clock circuitry.
Abstract:
Technologies are described which permit kernel updates or firmware fixes, and include re-initialization of kernel data structures, without losing user context information that has been created by services, virtual machines, or user applications. Tailored code in a server or other computing system sets a kernel soft reset (KSR) indicator and saves the user context to non-volatile storage. When a KSR is underway, boot code skips the power on self-test and similar initializations (thereby reducing downtime), loads a kernel image, initializes kernel data structures, restores the user context, and passes control to the initialized kernel to continue computing system operation with the same user context. Device drivers may also be re-initialized. The loaded kernel may use newly fixed firmware, or may have a security patch installed, for instance. The non-volatile storage may operate at RAM speed, e.g., it may include NVDIMM memory. The kernel may be validated before receiving control.
Abstract:
Embodiments of memory backup management in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method of managing memory backup includes in response to a system error being detected, causing a memory controller to disengage from communicating with and controlling a hybrid memory device having a volatile memory module and a non-volatile memory module. The method can also include causing the hybrid memory device to copy data from the volatile memory module to the non-volatile memory module subsequent to disengaging the memory controller communicating with and controlling the storage device and without operating the main processor and the memory controller.
Abstract:
Aspects extend to methods, systems, and computer program products for remediating power loss at a server. Aspects of the invention increase the likelihood of gracefully shutting down a server and associated components in a data center when mains power is lost for a specified amount of time (e.g., an amount of time beyond transition to generator power). A server can include a management module (e.g., a BMC) and a watchdog module. When the management controller detects loss of power at a power supply unit, the management controller orchestrates a graceful shutdown of the server in response to power loss. When the management module is unresponsive, the watchdog module provides backup functionality for orchestrating a graceful shutdown in response to power loss. As such, data can be saved from RAM to more durable storage even when the management module is unresponsive.
Abstract:
A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A maximum number of pages that may be treated as non-volatile may be determined based on an amount of energy available in a battery and an amount of energy needed to transfer a page of memory to the non-volatile storage device.
Abstract:
Various techniques for managing power backup for computing devices are disclosed herein. In one embodiment, a method includes receiving data representing a backup capacity of one or more backup power units and data representing a backup power profile of one or more processing units sharing the one or more backup power units. A portion of the backup capacity may then be assigned to each of the one or more processing units based at least in part on both the received data representing the backup capacity of the one or more backup power units and the received data representing the profile of the one or more processing units.
Abstract:
A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.
Abstract:
A fuel cell power controller tracks load current and fuel cell output voltage, and alerts on excessive fuel cell ramp rate, so another power source can supplement the fuel cell and/or the load can be reduced. A power engineering process makes efficient use of available fuel cell power by ramping up power flow rapidly when power is available, while respecting the ramp rate and other power limitations of the fuel cell and safety limitations of the load. Power flow decreases after an alert indicating an electrical output limitation of the fuel cell. Permitted power flow increases in response to a power demand increase (actual or requested) from the load in the absence of the alert. Power flow may increase or decrease in a fixed amount, a proportional amount, or per a sequence. A power controller relay may trip open on a low fuel cell output voltage or high load current.
Abstract:
A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger controller sends a data save command toward coupled volatile memory device(s) such as NVDIMMs and PCIe devices under specified conditions: a programmable amount of time passes without AC power, a voltage level drops below normal but is still sufficient to power the volatile memory device during a data save operation, the trigger controller is notified of an operating system shutdown command, or the trigger controller is notified of an explicit data save command without a system shutdown command. NVDIMMs can avoid reliance on dedicated supercapacitors and dedicated batteries. An NVDIMM may perform an asynchronous DRAM reset in response to the data save command. Voltage step downs may be coordinated among power supplies. After data is saved, power cycles and the system reboots.