公开(公告)号：WO2018044368A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/033300

申请日：2017-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ZHOU, Zhenming ,  LIANG, Guirong ,  HEMINK, Gerrit Jan ,  LEE, Dana ,  GORLA, Chandu ,  PUTHENTHERMADAM, Sarath ,  DUTTA, Deepanshu

IPC: G11C16/04 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3427

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for state-dependent read compensation. A set of non-volatile storage cells 200 comprises a plurality of word lines 260, 262, 264, 266, 506, 508, 510. A controller 126, 220 is configured to perform a read operation on one or more word lines 260, 262, 264, 266, 508, 510 adjacent to a target word line 506. A controller 126, 220 is configured to determine a read setting for application to a target word line 506 based on a result of a read operation on one or more word lines 260, 262, 264, 266, 508, 510 adjacent to the target word line 506. A controller 126, 220 is configured to perform a read operation on a target word line 506 using a determined read setting.

Abstract translation: 公开了用于状态相关读取补偿的设备，系统，方法和计算机程序产品。 一组非易失性存储单元200包括多个字线260,262,264,266,506,508,510。控制器126,220被配置为对一个或多个字线260,262执行读操作 控制器126,220被配置为基于在一个或多个字线506上的读取操作的结果来确定用于施加到目标字线506的读取设置 邻近目标字线506的控制器260,262,264,266,508,510。控制器126,220被配置为使用确定的读取设置对目标字线506执行读取操作。

公开(公告)号：WO2018038786A1

公开(公告)日：2018-03-01

申请号：PCT/US2017/035024

申请日：2017-05-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ZHANG, Yanli ,  ALSMEIER, Johann ,  KAI, James

IPC: H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/26513 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A buried source semiconductor layer and p-doped semiconductor material portions are formed over a first portion of a substrate. The buried source semiconductor layer is an n- doped semiconductor material, and the p-doped semiconductor material portions are embedded within the buried source semiconductor layer. An alternating stack of insulating layers and spacer material layers is formed over the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. The buried source semiconductor layer may be formed prior to, or after, formation of the alternating stack. The buried source semiconductor layer underlies the alternating stack and overlies the first portion of the substrate, and contacts at least one surface of the vertical semiconductor channels. The p-doped semiconductor material portions contact at least one surface of a respective subset of the vertical semiconductor channels.

Abstract translation: 掩埋源极半导体层和p掺杂半导体材料部分形成在衬底的第一部分之上。 掩埋源极半导体层是n-掺杂半导体材料，并且p-掺杂半导体材料部分嵌入掩埋源极半导体层内。 在衬底上形成交替的绝缘层和间隔材料层的叠层。 存储器堆栈结构通过交替堆栈形成。 间隔物材料层形成为导电层或被导电层取代。 掩埋源极半导体层可以在形成交替堆叠之前或之后形成。 掩埋源极半导体层位于交替堆叠之下并且覆盖衬底的第一部分，并接触垂直半导体沟道的至少一个表面。 p-掺杂半导体材料部分接触垂直半导体沟道的相应子集的至少一个表面。

公开(公告)号：WO2018009175A1

公开(公告)日：2018-01-11

申请号：PCT/US2016/041059

申请日：2016-07-06

Applicant: INTEL CORPORATION

Inventor： MAJHI, Prashant ,  KARPOV, Elijah

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/66 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/0466 ,  H01L27/11524 ,  H01L29/785 ,  H01L29/7881

Abstract: A high speed single transistor suitable for a non-volatile memory cell is described. In one example, the memory cell has a source, a drain coupled to the source through a gate channel, a gate coupled to the gate channel, a floating gate between the gate and the gate channel, and a threshold switch between the floating gate and the gate channel.

Abstract translation: 描述适用于非易失性存储器单元的高速单晶体管。 在一个示例中，存储器单元具有源极，通过栅极沟道耦合到源极的漏极，耦合到栅极沟道的栅极，在栅极和栅极沟道之间的浮动栅极，以及在浮动栅极和 门通道。

公开(公告)号：WO2016164318A1

公开(公告)日：2016-10-13

申请号：PCT/US2016/025916

申请日：2016-04-04

Applicant: NEO SEMICONDUCTOR, INC.

Inventor： HSU, Fu-Chang

IPC: H01L29/788 ,  H01L29/792

CPC classification number: G11C16/0433 ,  G11C16/0466 ,  G11C16/06 ,  G11C16/10 ,  H01L27/1157

Abstract: A two transistor SONOS flash memory is disclosed. In one aspect, an apparatus, includes a control gate transistor having source and drain diffusions deposited in an N-well, a charge-trapping region formed on the N-well that overlaps the source and drain diffusions, and a control gate formed on the charge-trapping region. A channel region of the N-well between the source and drain diffusions is less than 90nm in length. The apparatus also includes a select gate transistor having a select source diffusion deposited in the N-well. A drain side of the select gate transistor shares the source diffusion. A channel region of the N-well between the select source diffusion and the source diffusion also is less than 90nm in length.

Abstract translation: 公开了一种双晶体管SONOS闪速存储器。 一方面，一种装置包括：控制栅极晶体管，其具有沉积在N阱中的源极和漏极扩散层;形成在与所述源极和漏极扩散器重叠的所述N阱上的电荷俘获区域;以及控制栅极， 电荷捕获区域。 源极和漏极扩散之间的N阱的沟道区域的长度小于90nm。 该装置还包括具有沉积在N阱中的选择源扩散的选择栅极晶体管。 选择栅极晶体管的漏极侧共享源极扩散。 选择源扩散和源极扩散之间的N阱的沟道区域的长度小于90nm。

公开(公告)号：WO2016160669A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/024456

申请日：2016-03-28

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Xia ,  LU, Xiao ,  CHEN, Xiaonan ,  WANG, Zhongze ,  YEAP, Choh, Fei

IPC: H01L27/105 ,  G11C16/04

CPC classification number: H03K17/687 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/1052 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/792

Abstract: Aspects disclosed in the detailed description include high-k (HK)/metal gate (MG) (HK/MG) multi-time programmable (MTP) switching devices, and related systems and methods. One type of HK/MG MTP switching device is an MTP metal-oxide semiconductor (MOS) field-effect transistor (MOSFET). When the MTP MOSFET is programmed, a charge trap may build up in the MTP MOSFET due to a switching electrical current induced by a switching voltage. The charge trap reduces the switching window and endurance of the MTP MOSFET, thus reducing reliability in accessing the information stored in the MTP MOSFET. In this regard, an HK/MG MTP switching device comprising the MTP MOSFET is configured to eliminate the switching electrical current when the MTP MOSFET is programmed. By eliminating the switching electrical current, it is possible to avoid a charge trap in the MTP MOSFET, thus restoring the switching window and endurance of the MTP MOSFET for reliable information access.

Abstract translation: 在详细描述中公开的方面包括高k（HK）/金属门（MG）（HK / MG）多时间可编程（MTP）交换设备以及相关的系统和方法。 一种类型的HK / MG MTP开关器件是MTP金属氧化物半导体（MOS）场效应晶体管（MOSFET）。 当编程MTP MOSFET时，由于开关电压引起的开关电流，电荷陷阱可能会积累在MTP MOSFET中。 电荷阱减少了MTP MOSFET的开关窗口和耐久性，从而降低了访问存储在MTP MOSFET中的信息的可靠性。 在这方面，包括MTP MOSFET的HK / MG MTP开关器件被配置为在编程MTP MOSFET时消除开关电流。 通过消除开关电流，可以避免MTP MOSFET中的电荷陷阱，从而恢复MTP MOSFET的开关窗口和耐用性，从而实现可靠的信息访问。

公开(公告)号：WO2016130192A1

公开(公告)日：2016-08-18

申请号：PCT/US2015/062621

申请日：2015-11-25

Applicant: SanDisk Technologies LLC

Inventor： DUTTA, Deepanshu ,  LEE, Shih-Chung

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/345

Abstract: Reducing peak current and/or power consumption during verify of a non-volatile memory is disclosed. During an erase verify, memory cells are verified at a strict reference level that is deeper (e.g., lower threshold voltage) than a target reference level. After the strict erase verify, strings of memory cells that pass the strict erase verify are locked out from a next erase verify at the target reference level. Locked out strings do not conduct a significant current during verify, thus reducing current/power consumption

Abstract translation: 公开了在验证非易失性存储器期间降低峰值电流和/或功率消耗。 在擦除验证期间，在比目标参考电平更深（例如，较低阈值电压）的严格参考电平处验证存储器单元。 在严格擦除验证之后，通过严格擦除验证的存储单元串被锁定在目标参考电平的下一次擦除验证。 锁定字符串在验证期间不会导致显着的电流，从而降低电流/功耗

公开(公告)号：WO2016064772A1

公开(公告)日：2016-04-28

申请号：PCT/US2015/056294

申请日：2015-10-20

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： KELLY, Bryan ,  GOVINDAN, Sriram ,  SIEGLER, John J. ,  KHESSIB, Badriddine ,  SHAW, Mark A. ,  ANDREWARTHA, J. Michael

IPC: G06F1/30 ,  G06F11/14

CPC classification number: G11C14/0018 ,  G06F1/28 ,  G06F1/30 ,  G06F11/1441 ,  G06F11/1456 ,  G06F11/2015 ,  G06F13/4068 ,  G06F13/4282 ,  G11C5/148 ,  G11C14/009 ,  G11C16/0466 ,  Y02D10/14 ,  Y02D10/151

Abstract: A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger controller sends a data save command toward coupled volatile memory device(s) such as NVDIMMs and PCIe devices under specified conditions: a programmable amount of time passes without AC power, a voltage level drops below normal but is still sufficient to power the volatile memory device during a data save operation, the trigger controller is notified of an operating system shutdown command, or the trigger controller is notified of an explicit data save command without a system shutdown command. NVDIMMs can avoid reliance on dedicated supercapacitors and dedicated batteries. An NVDIMM may perform an asynchronous DRAM reset in response to the data save command. Voltage step downs may be coordinated among power supplies. After data is saved, power cycles and the system reboots.

Abstract translation: 易失性存储器数据保存子系统可以包括与诸如机箱或机架电池或发电机的共享电源的耦合。 数据保存触发器控制器在指定条件下向诸如NVDIMM和PCIe设备之类的耦合的易失性存储器件发送数据保存命令：可编程的时间经过没有交流电源，电压电平降低到正常值以下但是仍然足以供电 在数据保存操作期间的易失性存储器件，触发控制器被通知操作系统关机命令，或者触发控制器被通知明确的数据保存命令而没有系统关机命令。 NVDIMM可以避免对专用超级电容器和专用电池的依赖。 响应于数据保存命令，NVDIMM可以执行异步DRAM重置。 在电源之间可以协调电压降档。 保存数据后，电源循环并重新启动系统。

公开(公告)号：WO2015171235A1

公开(公告)日：2015-11-12

申请号：PCT/US2015/024589

申请日：2015-04-06

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： PANG, Liang ,  CHEN, Hong-Yan ,  DONG, Yingda

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459

Abstract: Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution. Detrapping is particularly problematic for charge-trapping memory cells such as in a 3D stacked non-volatile memory device. During programming, a temporary lockout mode is provided for memory cells which pass a verify test. During a checkpoint program-verify iteration, all memory cells of a target data state are subject to the verify test. The memory cells in the temporary lockout mode are therefore subject to the verify test a second time. Memory cells that fail the verify test in the checkpoint program-verify iteration are programmed further. A normal or slow programming mode is used for a memory cell depending on whether it had reached the temporary lockout mode. Threshold voltage distributions are narrowed by reprogramming some of the memory cells.

Abstract translation: 提供了用于对存储器单元进行编程的技术，同时减少了导致阈值电压分布中的降档的去饱和效应。 解扣对于诸如在3D堆叠的非易失性存储器件中的电荷捕获存储器单元是特别有问题的。 在编程期间，为通过验证测试的存储器单元提供临时锁定模式。 在检查点程序验证迭代期间，目标数据状态的所有存储单元都进行验证测试。 因此，临时锁定模式中的存储单元第二次进行验证测试。 在检查点程序验证迭代中验证测试失败的内存单元进一步编程。 根据存储单元是否达到临时锁定模式，正常或慢速编程模式被用于存储单元。 通过重新编程某些存储器单元，阈值电压分布变窄。

公开(公告)号：WO2014110123A1

公开(公告)日：2014-07-17

申请号：PCT/US2014/010664

申请日：2014-01-08

Applicant: SANDISK TECHNOLOGIES,INC.

Inventor： DUTTA, Deepanshu ,  LI, Yan ,  HIGASHITANI, Masaaki ,  DUNGA, Mohan

IPC: G11C16/14 ,  G11C16/34

CPC classification number: G11C16/3445 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/3418 ,  G11C16/3436 ,  G11C16/349 ,  H01L27/0255

Abstract: Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device. When an erase command is made to erase memory cells, the select gate transistors are read to determine whether their Vth is above an acceptable range. If their Vth is above the acceptable range, the select gate transistors can be erased concurrently with the erasing of the memory cells.

Abstract translation: 提供了与一组存储器单元的编程或擦除有关的选择栅极晶体管的编程和擦除的技术。 响应于编程存储器单元的编程命令，读取选择栅晶体管以确定它们的Vth是否低于可接受的范围，在这种情况下，选择栅极晶体管在存储单元之前被编程。 或者，可以基于编程擦除周期的计数，无论是否经过了指定的时间段和/或非易失性存储设备的温度历史，可以决定编程选择栅极晶体管。 当擦除存储器单元的擦除命令时，读取选择栅极晶体管以确定它们的Vth是否高于可接受的范围。 如果它们的Vth高于可接受的范围，则选择栅极晶体管可以与存储器单元的擦除同时擦除。

公开(公告)号：WO2012136206A3

公开(公告)日：2012-12-13

申请号：PCT/DE2012200019

申请日：2012-03-29

Applicant: UNIV BERLIN TECH ,  MARENT ANDREAS ,  BIMBERG DIETER

Inventor： MARENT ANDREAS ,  BIMBERG DIETER

IPC: H01L29/80 ,  B82Y10/00 ,  G11C16/04 ,  H01L29/788

CPC classification number: G11C16/0466 ,  B82Y10/00 ,  G11C16/0408 ,  G11C16/14 ,  G11C16/26 ,  H01L29/788 ,  H01L29/803

Abstract: The invention relates to a memory cell (10) comprising at least one binary memory area for storing an item of bit information and to a method for storing an item of bit information. According to the invention, it is provided that the memory area (SB), e.g. a quantum dot layer of In(Ga)As quantum dots, can optionally store holes or electrons and allows a recombination of holes and electrons, the charge carrier type of the charge carriers stored in the memory area defines the bit information of the memory area and a charge carrier injection device (PN) is present, by means of which optionally holes or electrons can be injected into the memory area (SB) and the bit information can thus be changed. The holes and electrons come from a hole reservoir (LR) or electron reservoir (ER) which consist e.g. of p-doped or n-doped GaAs. The readout layer (AS) is a two-dimensional hole or electron gas layer.

Abstract translation: 本发明涉及一种具有用于存储位信息的至少一个二进制存储区域的存储单元（10），以及用于存储Bitinfomation的方法。 根据本发明，它提供的是，存储器区域（SB），例如。 例如，在量子点层（Ga）的量子点，wahl¬例如可以存储空穴或电子和空穴和电子的重组允许存储在载流子的存储区域中的数据的电荷载流子确定的存储器区域的所述位信息，并提供一个电荷载流子注入装置（PN） 是，与可选的空穴或电子到存储器区域（SB）可以被注入，从而将位可被改变。 空穴和电子从空穴（LR）或电子储存器（ER），其例如源于 由p型或n型掺杂的GaAs构成。 读出层（AS）是一二维空穴或电子气层。