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公开(公告)号：WO2017158678A1
公开(公告)日：2017-09-21
申请号：PCT/JP2016/057961
申请日：2016-03-14
Applicant: オリンパス株式会社
IPC: H04N5/3745 , H03M1/10 , H03M1/38 , H03M1/74 , H04N9/07
CPC classification number: H03M1/466 , H03M1/123 , H03M1/468 , H04N5/3742 , H04N5/37455 , H04N5/378 , H04N9/0455
Abstract: ＡＤ変換器は、第１のＤＡＣ回路と、第２のＤＡＣ回路と、比較回路と、制御回路とを有する。前記第１のＤＡＣ回路は、前記第２のＤＡＣ回路による第２の動作と並行して第１の動作を行い、かつ前記第１のＤＡＣ回路は、前記第２のＤＡＣ回路による前記第１の動作と並行して前記第２の動作を行う。前記第１の動作において、前記第１のＤＡＣ回路または前記第２のＤＡＣ回路の入力信号に応じた電荷がサンプリングされる。前記第２の動作において、前記第１の動作によりサンプリングされた電荷に基づいて順次ＡＤ変換が行われる。前記第１のＤＡＣ回路および前記第２のＤＡＣ回路は、前記第１の動作および前記第２の動作を交互に行う。
Abstract translation:
AD转换器包括：第一DAC电路，第二DAC电路，比较电路，以及控制电路。 第一DAC电路，所述通过在平行第二DAC电路与所述第二操作被执行的第一操作，和第一DAC电路，首先由第二DAC电路 与该操作并行地，执行第二操作。 在第一操作中，对应于DAC电路或第二DAC电路的输入信号中的第一电荷进行采样。 在第二操作中，基于通过第一操作采样的电荷顺序地执行AD转换。 第一DAC电路和第二DAC电路交替执行第一操作和第二操作。
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公开(公告)号：WO2017158677A1
公开(公告)日：2017-09-21
申请号：PCT/JP2016/057956
申请日：2016-03-14
Applicant: オリンパス株式会社
Inventor： 大澤 雅人
IPC: H04N5/3745 , H03M1/10 , H03M1/38 , H03M1/74
Abstract: ＡＤ変換器は、第１のＤＡＣ回路と、第２のＤＡＣ回路と、比較回路と、制御回路と、制御スイッチとを有する。前記比較回路は、前記第１のＤＡＣ回路の第１の出力ノードおよび前記第２のＤＡＣ回路の第２の出力ノードに接続され、かつ前記第１の出力ノードおよび前記第２の出力ノードの電位を比較する。前記制御回路は、前記比較回路の比較結果に応じて、前記第１のＤＡＣ回路および前記第２のＤＡＣ回路を制御する。前記制御スイッチは、前記第１のＤＡＣ回路の第１の入力ノードと前記第２のＤＡＣ回路の第２の入力ノードとの接続のオンおよびオフを制御する。
Abstract translation: AD转换器具有第一DAC电路，第二DAC电路，比较电路，控制电路和控制开关。 其中比较电路连接到第一DAC电路的第一输出节点和第二DAC电路的第二输出节点，并具有第一输出节点和第二输出节点的电位 比较。 控制电路根据比较电路的比较结果来控制第一DAC电路和第二DAC电路。 控制开关控制第一DAC电路的第一输入节点和第二DAC电路的第二输入节点之间的连接的接通和断开。
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公开(公告)号：WO2017025844A1
公开(公告)日：2017-02-16
申请号：PCT/IB2016/054495
申请日：2016-07-28
Applicant: KONINKLIJKE PHILIPS N.V.
Inventor： CHAPPO, Marc Anthony
Abstract: A detector array (112) of an imaging system (100)includes a radiation sensitive detector (202/204/206) configured to detect radiation and generates a signal indicative thereof and electronics (208) in electrical communication with the radiation sensitive detector. The electronics include a current-to-frequency converter (300) configured to convert the signal into a pulse train having a frequency indicative of a charge collected during an integration period. The electronics further include a residual charge collection circuit (322) electrically coupled to current-to-frequency converter. The residual charge collection circuit is configured to store charge collected by the integrator for an end portion of the integration period that does not results in a pulse of the pulse train, utilizing much of the electronics already in the current-to-frequency converter electronics.
Abstract translation: 成像系统（100）的检测器阵列（112）包括被配置为检测辐射并产生指示信号的辐射敏感检测器（202/204/206）和与辐射敏感检测器电连通的电子器件（208）。 电子设备包括电流 - 频率转换器（300），其被配置为将信号转换成具有指示在积分周期期间收集的电荷的频率的脉冲串。 电子设备还包括电耦合到电流 - 频率转换器的剩余电荷收集电路（322）。 剩余电荷收集电路被配置为存储积分器收集的电荷，用于不产生脉冲序列的脉冲的积分周期的端部，利用电流到频率转换器电子器件中的大部分电子器件。
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公开(公告)号：WO2016017898A1
公开(公告)日：2016-02-04
申请号：PCT/KR2015/003547
申请日：2015-04-09
Applicant: 중앙대학교 산학협력단
IPC: H03M1/38
CPC classification number: H03M1/38 , H03M1/1245 , H03M1/466 , H03M1/468 , H03M1/68
Abstract: 분리 형태의 듀얼 캐패시터 어레이를 가지는 연속 근사 레지스터 아날로그 디지털 변환기가 개시된다. 개시된 연속 근사 레지스터 아날로그 디지털 변환기는 n 비트 중에서, 상위 비트들을 변환하기 위한 제1 캐패시터 어레이 및 하위 비트들을 변환하기 위한 제2 캐패시터 어레이를 포함하는 듀얼 캐패시터 어레이; 상기 제1 캐패시터 어레이에서 출력된 레벨 신호 및 상기 제2 캐패시터 어레이에서 출력된 레벨 신호를 비교하는 비교기; 및 상기 비교 결과를 이용하여 아날로그 입력 전압을 상기 n 비트의 디지털 신호로 변환하는 SAR 논리 회로;를 포함하되, 상기 제1 캐패시터 어레이는 제1-1 캐패시터부 및 제1-2 캐패시터부를 포함하고, 상기 제2 캐패시터 어레이는 제2-1 캐패시터부 및 제2-2 캐패시터부를 포함하되, 상기 캐패시터부 각각은 병렬 연결된 복수의 캐패시터를 포함한다.
Abstract translation: 公开了具有可分离双电容器阵列的逐次逼近电阻模数转换器。 所公开的逐次逼近模数转换器包括：双电容器阵列，包括用于转换n位中的高位的第一电容器阵列和用于从n位转换低位的第二电容器阵列; 比较器，用于比较从第一电容器阵列输出的电平信号和从第二电容器阵列输出的电平信号; 以及SAR逻辑电路，用于通过利用比较结果将模拟输入电压转换成n位的数字信号，其中第一电容器阵列包括1-1电容器单元和1-2电容器单元，第二电容器 阵列包括2-1电容器单元和2-2电容器单元，每个电容器单元包括并联连接的多个电容器。
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5.发明申请A SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION ARCHITECTURAL ARRANGMENT FOR RECEIVERS 审中-公开接收端的连续逼近模拟到数字转换架构设计
公开(公告)号：WO2014110315A1
公开(公告)日：2014-07-17
申请号：PCT/US2014/010963
申请日：2014-01-10
Applicant: INTEL CORPORATION , COWLEY, Nicholas P. , ALI, Isaac , SUETINOV, Viatcheslav I. , PINSON, Keith
Inventor： COWLEY, Nicholas P. , ALI, Isaac , SUETINOV, Viatcheslav I. , PINSON, Keith
IPC: H03M1/12
CPC classification number: H03M1/0626 , H03M1/466
Abstract: An apparatus and method of successive approximation analog-to-digital conversion for receivers comprising that during a sample mode, connecting an array of capacitors to a plurality of sampling switches coupled to a plurality of amplified input signals, and during a conversion mode, connecting in common the array of capacitors to a comparator and isolating the array of capacitors from the plurality of sampling switches. Additionally, filtering is done by the summation of samples at phase offsets.
Abstract translation: 一种用于接收机的逐次逼近模数转换的装置和方法，包括在采样模式期间，将电容器阵列连接到耦合到多个放大输入信号的多个采样开关，并且在转换模式期间，连接到 将电容器阵列与比较器共用，并将电容器阵列与多个采样开关隔离。 另外，通过相位偏移处的样本的求和来进行滤波。
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Patent Agency Ranking6.发明申请
公开(公告)号：WO2011151671A1
公开(公告)日：2011-12-08
申请号：PCT/IB2010/002919
申请日：2010-11-17
Inventor： BAGHINI, Maryam, Shojaei , HANDE, Vinayak, Gopal
CPC classification number: H03M1/466
Abstract: Techniques are generally described herein for analog to digital conversion. Some example ADC converters include a unit capacitor array coupled to a reference voltage, where the capacitor array includes multiple capacitors coupled to one another via multiple switches under control of a control block. A comparator, having a first input and a second input, is configured to receive a controlled voltage generated from the unit capacitor array and compare an analog voltage to the controlled voltage. The control block is configured to selectively open or close the switches, receive a comparison result from the comparator, and generate a digital output based on the comparison result. The control block is configured to control the switch timing of the unit capacitor array for reset, pre-charge, charge redistribution, and comparison phases, where a passive charge redistribution method may be utilized.
Abstract translation: 这里通常描述用于模数转换的技术。 一些示例ADC转换器包括耦合到参考电压的单元电容器阵列，其中电容器阵列包括通过控制块控制下的多个开关彼此耦合的多个电容器。 具有第一输入和第二输入的比较器被配置为接收从单位电容器阵列产生的受控电压并将模拟电压与受控电压进行比较。 控制块被配置为选择性地打开或关闭开关，从比较器接收比较结果，并且基于比较结果生成数字输出。 控制块被配置为控制用于复位，预充电，电荷再分配和比较阶段的单位电容器阵列的开关定时，其中可以使用无源电荷再分配方法。
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公开(公告)号：WO99062120A1
公开(公告)日：1999-12-02
申请号：PCT/US1999/011006
申请日：1999-05-18
CPC classification number: H03M1/466 , H01L27/0805 , H03M1/0602 , H03M1/46 , H03M1/806
Abstract: A capacitor array layout technique for improving capacitor array matching. A capacitor array is laid out in a geometrical configuration wherein the geometrical configuration has a centerpoint. The geometrical configuration is divided into a plurality of first sections wherein each of the plurality of first sections have a corresponding second section diagonally located from and at an approximately equal distance from the centerpoint as said first section. Each of the second sections house a capacitor set of a predetermined value wherein each of the plurality of first sections house a capacitor set of an equal value as the corresponding second section.
Abstract translation: 一种用于改善电容器阵列匹配的电容器阵列布局技术。 电容器阵列以几何构型布置，其中几何构型具有中心点。 所述几何构造被分成多个第一部分，其中所述多个第一部分中的每一个具有相应的第二部分，所述对应的第二部分在所述第一部分处与所述中心点对角定位并且距离所述中心点大致相等。 每个第二部分容纳预定值的电容器组，其中多个第一部分中的每一个容纳与相应的第二部分相等的电容器组。
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公开(公告)号：WO2018094579A1
公开(公告)日：2018-05-31
申请号：PCT/CN2016/106826
申请日：2016-11-22
Applicant: 深圳市汇顶科技股份有限公司
CPC classification number: G06K9/0002 , G06F3/0416 , G06F3/044 , G11C27/024 , H03K17/962 , H03K17/9622 , H03K2217/960725 , H03K2217/96074 , H03M1/466 , H03M1/66
Abstract: 一种电容感测电路(10)，包括一积分电路(12)，包含有一积分输入端，耦接于接触电容(Cf)，所述积分输入端具有一输入电压(Vx)；以及一积分输出端，用来输出一输出电压(Vo)；一比较器(Comp)；一正向数模转换单元(14a)；一负向数模转换单元(14b)；一控制电路(16)，用来控制所述正向数模转换单元(14a)以及所述负向数模转换单元(14b)；以及一逻辑电路(18)，用来输出一输出码(c total )，所述输出码(c total )相关于所述接触电容(Cf)的一电容值。
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9.发明申请
公开(公告)号：WO2017046782A1
公开(公告)日：2017-03-23
申请号：PCT/IB2016/055590
申请日：2016-09-19
Inventor： OMRAN, Hesham , ALHOSHANY, Abdulaziz , SALAMA, Khaled
CPC classification number: G01D5/24 , G01R27/2605 , H03M1/1009 , H03M1/466
Abstract: An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog- to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter- based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.
Abstract translation: 提供了一种利用电容域逐次逼近（SAR）技术的节能电容数字转换器（CDC）。 与SAR模数转换器（ADC）不同，分析表明，对于SAR CDC，比较器偏移电压将导致信号相关和寄生相关的转换误差，这就需要基于运算放大器的实现。 本文考虑的基于逆变器的SAR CDC提供了强大的，节能的和快速的操作。 基于逆变器的SAR CDC可以包括混合粗略可编程电容器阵列。 示例实施例的设计对模拟参考不敏感，因此在不需要校准的情况下实现非常低的温度灵敏度。 此外，该设计实现了能量效率的提高。
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公开(公告)号：WO2016087869A1
公开(公告)日：2016-06-09
申请号：PCT/GB2015/053708
申请日：2015-12-03
Applicant: ATLANTIC INERTIAL SYSTEMS LIMITED
Inventor： DURSTON, Michael Terrence , TOWNSEND, Kevin , SITCH, Douglas Robert
Abstract: A successive approximation Analogue to Digital Converter (ADC), comprising: a sample and hold device arranged to sample and hold an input signal at the beginning of a conversion cycle; a successive approximation register that sequentially builds up a digital output from its most significant bit to its least significant bit; a digital to analogue converter that outputs a signal based on the output of the successive approximation register; a comparator that compares the output of the digital to analogue converter with an output of the sample and hold device and supplies its output to the successive approximation register; and a residual signal storage device arranged to store the residual signal at the end of a conversion cycle; and wherein the successive approximation ADC is arranged to add the stored residual signal from the residual signal storage device to the input signal stored on the sample and hold device at the start of each conversion cycle. After each ADC full conversion by the SAR, the analogue conversion of the digital output is as close to the original input signal as the resolution will allow. However there remains the residual part of the input signal that is smaller than what can be represented by the least significant bit of the digital output of the SAR. In normal operation, successive outputs of a SAR for the same input will result in the same digital value output and the same residual. By storing the residual at the end of each conversion and adding the residual onto the input signal of the next conversion the residuals are accumulated over time so that they may affect the output digital value. After a number of conversions, the accumulated residuals add up to more than the value represented by the LSB of the register and the digital value will be one higher than if a conversion had been performed on the input signal alone. In this way, the residual signal affects the output value in time and thus can be taken into account by processing the digital output in the time domain.
Abstract translation: 一种逐次逼近的模数转换器（ADC），包括：采样和保持装置，被布置成在转换周期开始时对输入信号进行采样和保持; 逐次逼近寄存器，从最高有效位到其最低有效位顺序建立数字输出; 数模转换器，其基于逐次逼近寄存器的输出输出信号; 比较器，将数模转换器的输出与采样和保持装置的输出进行比较，并将其输出提供给逐次逼近寄存器; 以及残余信号存储装置，被布置成在转换周期结束时存储所述残余信号; 并且其中所述逐次逼近ADC被布置为在每个转换周期开始时将存储的残留信号从残留信号存储装置添加到存储在采样和保持装置上的输入信号。 在通过SAR进行每次ADC完全转换后，数字输出的模拟转换与分辨率允许的原始输入信号相近。 然而，输入信号的剩余部分仍然比由SAR的数字输出的最低有效位表示的少。 在正常操作中，相同输入的SAR的连续输出将导致相同的数字值输出和相同的残差。 通过在每个转换结束时存储残差，并将残差加到下一转换的输入信号上，残差随着时间的推移而累积，从而可能影响输出数字值。 经过多次转换后，累计残差加起来高于寄存器LSB的值，数字值比单独输入信号进行转换时要高一个。 以这种方式，残留信号及时影响输出值，因此可以通过在时域中处理数字输出来考虑。
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