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    VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES
    2.
    发明申请
    VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES 审中-公开

    公开(公告)号：WO2020036917A1

    公开(公告)日：2020-02-20

    申请号：PCT/US2019/046275

    申请日：2019-08-13

    Applicant: OPTIMUM SEMICONDUCTOR TECHNOLOGIES INC.

    Inventor： MOUDGILL, Mayan ,  GLOSSNER, John

    IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16

    Abstract: A processor including a vector register file comprising a plurality of vector registers, at least one buffer register, and a vector processing core, communicatively connected to the vector register file and the at least one buffer register, to receive a vector instruction comprising a first identifier representing a first vector register of the plurality of vector registers, and a second identifier representing a second vector register of the plurality of vector registers, wherein the first vector register is a source register and the second vector register is a destination register, execute the vector instruction based on data values stored in the first vector register to generate a result and store the result in the at least one buffer register, and responsive to determining that the second vector register is safe to write, copy the result from the at least one buffer register to the second vector register.

    IMPLEMENTATION OF REGISTER RENAMING, CALL-RETURN PREDICTION AND PREFETCH
    6.
    发明申请
    IMPLEMENTATION OF REGISTER RENAMING, CALL-RETURN PREDICTION AND PREFETCH 审中-公开

    公开(公告)号：WO2018132652A1

    公开(公告)日：2018-07-19

    申请号：PCT/US2018/013480

    申请日：2018-01-12

    Applicant: OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.

    Inventor： MOUDGILL, Mayan ,  NACER, Gary ,  HOANE, A., Joseph ,  HURTLEY, Paul ,  SENTHILVELAN, Murugappan

    IPC: G06F9/30

    Abstract: A processor includes a plurality of physical registers and a processor core, communicatively coupled to the plurality of physical registers, the processor core to execute a process comprising a plurality of instructions to responsive to issuance of a call instruction for out-of-order execution, identify, based on a head pointer of the plurality of physical registers, a first physical register of the plurality of physical registers, store a return address in the first physical register, wherein the first physical register is associated with a first identifier, store, based on an out-of-order pointer of a call stack associated with the process, the first identifier in a first entry of the call stack, and increment, modulated by a length of the call stack, the out-of-order pointer of the call stack to point to a second entry of the call stack.

    PROCESSOR WITH ADVANCED OPERATING SYSTEM SUPPORT
    7.
    发明申请
    PROCESSOR WITH ADVANCED OPERATING SYSTEM SUPPORT 审中-公开
    具有高级操作系统支持的处理器

    公开(公告)号：WO2016200567A1

    公开(公告)日：2016-12-15

    申请号：PCT/US2016/032853

    申请日：2016-05-17

    Applicant: OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.

    Inventor： MOUDGILL, Mayan ,  NACER, Gary ,  GLOSSNER, C., John ,  HOANE, Arthur, Joseph ,  HURTLEY, Paul ,  SENTHILVELAN, Murugappan

    IPC: G06F9/46

    CPC classification number: G06F9/30189 ,  G06F9/3005 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/462

    Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include witching mode logic to switch between the first mode and the second mode.

    Abstract translation: 计算机处理器可以包括多个硬件线程。 计算机处理器还可以包括用于硬件线程的状态的状态处理器逻辑。 状态处理器逻辑可以包括每个线程逻辑，其包含在多个硬件线程的每个硬件线程中复制的状态和独立于多个硬件线程中的每个硬件线程的公共逻辑。 计算机处理器还可以包括单线程模式逻辑，以仅从多个硬件线程中的一个硬件线程以单线程模式执行指令。 计算机处理器可以进一步包括第二模式逻辑，以在多个硬件线程中的多于一个硬件线程同时执行第二模式中的指令。 计算机处理器还可以包括在第一模式和第二模式之间切换的巫术模式逻辑。

    DEVICE AND METHOD FOR CALCULATING ELEMENTARY FUNCTIONS USING SUCCESSIVE CUMULATIVE ROTATION CIRCUIT
    10.
    发明申请
    DEVICE AND METHOD FOR CALCULATING ELEMENTARY FUNCTIONS USING SUCCESSIVE CUMULATIVE ROTATION CIRCUIT 审中-公开

    公开(公告)号：WO2020172369A1

    公开(公告)日：2020-08-27

    申请号：PCT/US2020/018976

    申请日：2020-02-20

    Applicant: OPTIMUM SEMICONDUCTOR TECHNOLOGIES INC.

    Inventor： MOUDGILL, Mayan ,  BALZOLA, Pablo ,  SENTHIVELAN, Murugappan ,  RAMDURAI, Vaidyanathan ,  AGRAWAL, Sitij

    IPC: G06F1/02 ,  G06F1/06 ,  G06F7/499

    Abstract: A system and an accelerator circuit including a register file comprising instruction registers to store an instruction for evaluating an elementary function, and data registers comprising a first data register to store an input value. The accelerator circuit further includes a successive cumulative rotation circuit comprising a reconfigurable inner stage to perform a successive cumulative rotation recurrence, and a determination circuit to determine a type of the elementary function based on the instruction, and responsive to determining that the input value is a fixed-point number, configure the reconfigurable inner stage to a configuration for evaluating the type of the elementary function, wherein the successive cumulative rotation circuit is to calculate an evaluation of the elementary function using the reconfigurable inner stage performing the successive cumulative rotation recurrence.

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