公开(公告)号：WO2018132653A1

公开(公告)日：2018-07-19

申请号：PCT/US2018/013484

申请日：2018-01-12

Applicant: OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.

Inventor： MOUDGILL, Mayan ,  HOANE, A. Joseph ,  WANG, Lei ,  NACER, Gary ,  MILBURY, Aaron G. ,  BARRIA, Enrique A. ,  HURTLEY, Paul

IPC: G06F9/26 ,  G06F9/34

Abstract: A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual, memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.

公开(公告)号：WO2018132652A1

公开(公告)日：2018-07-19

申请号：PCT/US2018/013480

申请日：2018-01-12

Applicant: OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.

Inventor： MOUDGILL, Mayan ,  NACER, Gary ,  HOANE, A., Joseph ,  HURTLEY, Paul ,  SENTHILVELAN, Murugappan

IPC: G06F9/30

Abstract: A processor includes a plurality of physical registers and a processor core, communicatively coupled to the plurality of physical registers, the processor core to execute a process comprising a plurality of instructions to responsive to issuance of a call instruction for out-of-order execution, identify, based on a head pointer of the plurality of physical registers, a first physical register of the plurality of physical registers, store a return address in the first physical register, wherein the first physical register is associated with a first identifier, store, based on an out-of-order pointer of a call stack associated with the process, the first identifier in a first entry of the call stack, and increment, modulated by a length of the call stack, the out-of-order pointer of the call stack to point to a second entry of the call stack.

公开(公告)号：WO2016200567A1

公开(公告)日：2016-12-15

申请号：PCT/US2016/032853

申请日：2016-05-17

Applicant: OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.

Inventor： MOUDGILL, Mayan ,  NACER, Gary ,  GLOSSNER, C., John ,  HOANE, Arthur, Joseph ,  HURTLEY, Paul ,  SENTHILVELAN, Murugappan

IPC: G06F9/46

CPC classification number: G06F9/30189 ,  G06F9/3005 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/462

Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include witching mode logic to switch between the first mode and the second mode.

Abstract translation: 计算机处理器可以包括多个硬件线程。 计算机处理器还可以包括用于硬件线程的状态的状态处理器逻辑。 状态处理器逻辑可以包括每个线程逻辑，其包含在多个硬件线程的每个硬件线程中复制的状态和独立于多个硬件线程中的每个硬件线程的公共逻辑。 计算机处理器还可以包括单线程模式逻辑，以仅从多个硬件线程中的一个硬件线程以单线程模式执行指令。 计算机处理器可以进一步包括第二模式逻辑，以在多个硬件线程中的多于一个硬件线程同时执行第二模式中的指令。 计算机处理器还可以包括在第一模式和第二模式之间切换的巫术模式逻辑。

公开(公告)号：WO2016171866A1

公开(公告)日：2016-10-27

申请号：PCT/US2016/025279

申请日：2016-03-31

Applicant: OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.

Inventor： MOUDGILL, Mayan ,  NACER, Gary ,  GLOSSNER, C., John ,  HOANE, A., Joseph ,  HURTLEY, Paul ,  MURUGAPPAN, Senthilvelan ,  BALZOLA, Pablo

IPC: G06F9/355

CPC classification number: G06F9/30029 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0673 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/3013 ,  G06F9/322 ,  G06F9/355 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1009 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602

Abstract: A computer processor with an address register file is disclosed. The computer processor may include a memory. The computer processor may further include a general purpose register file comprising at least one general purpose register. The computer processor may further include an address register file comprising at least one address register. The computer processor may further include having access to the memory, the general purpose register file, and the address register file. The processing logic may execute a memory access instruction that accesses one or more memory locations in the memory at one or more corresponding addresses computed by retrieving the value of an address register of the at least one register of the address register file specified in the instruction and adding a displacement value encoded in the instruction.

Abstract translation: 公开了一种具有地址寄存器文件的计算机处理器。 计算机处理器可以包括存储器。 计算机处理器还可以包括包括至少一个通用寄存器的通用寄存器文件。 计算机处理器还可以包括包括至少一个地址寄存器的地址寄存器文件。 计算机处理器还可以包括访问存储器，通用寄存器文件和地址寄存器文件。 处理逻辑可以执行存储器访问指令，该存储器访问指令通过检索指令中指定的地址寄存器文件的至少一个寄存器的地址寄存器的值而计算的一个或多个对应地址访问存储器中的一个或多个存储器位置，以及 添加在指令中编码的位移值。