公开(公告)号：WO2012154589A1

公开(公告)日：2012-11-15

申请号：PCT/US2012/036621

申请日：2012-05-04

Applicant: OSTENDO TECHNOLOGIES, INC. ,  EL-GHOROURY, Hussein, S. ,  CHUANG, Chih-Li ,  YADAVALLI, Kameshwar ,  FAN, Qian

Inventor： EL-GHOROURY, Hussein, S. ,  CHUANG, Chih-Li ,  YADAVALLI, Kameshwar ,  FAN, Qian

IPC: H01S5/40 ,  H01L27/146 ,  H01L21/20 ,  H01L21/762

CPC classification number: H01L33/0079 ,  H01L21/187 ,  H01L27/14618 ,  H01L27/14683 ,  H01L33/0066 ,  H01L33/0095 ,  H01L2924/0002 ,  H01L2924/351 ,  H01L2933/0066 ,  H01L2924/00

Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods for bonding of semiconductor wafers incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed across the bonding surface using multiplicity of metal posts each comprised of multiple layers of metal that are interfused across the bonding surface. The optical vias are formed across the bonding surface using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers. The electrical and optical vias are interspersed across the bonding surface between the bonded wafers to enable uniform transfer of both electrical and optical signals between the bonded wafers.

Abstract translation: 用于接合半导体晶片的方法，其需要在接合的晶片之间并且跨接合界面传输电和光信号。 用于接合半导体晶片的方法包括在晶片接合界面内形成电和光互连通孔，以在接合的晶片之间转移电和光信号。 通过结合表面形成电通孔，使用多个金属柱，每个金属柱由跨接合表面的多层金属组成。 通过使用多个光波导形成光通孔，每个光波导由电介质材料构成，该电介质材料在接合界面之间相互连接并且具有高于接合晶片之间的电介质中间结合层的折射率的折射率 。 电通孔和光通孔穿过接合的晶片之间的结合表面，以使得能够在结合的晶片之间均匀地传递电信号和光信号。

公开(公告)号：WO2017106788A1

公开(公告)日：2017-06-22

申请号：PCT/US2016/067379

申请日：2016-12-16

Applicant: OSTENDO TECHNOLOGIES, INC.

Inventor： BATINICA, Gregory ,  YADAVALLI, Kameshwar ,  FAN, Qian ,  HASKELL, Benjamin A. ,  EL-GHOROURY, Hussein S.

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/06 ,  H01L21/20 ,  H01L21/38 ,  H01L21/67

CPC classification number: H01L21/02035 ,  H01L21/02002 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02172 ,  H01L21/02274 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/94 ,  H01L29/2003 ,  H01L29/30 ,  H01L2224/94 ,  H01L2924/3511

Abstract: A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.

Abstract translation: 一种改善半导体晶片平面度的方法和由该方法制成的组件。 在该方法的优选实施例中，具有预定厚度或图案的诸如SiO 2的压缩PECVD氧化物层被沉积在具有不希望的弯曲或弯曲的半导体晶片的第二表面上。 沉积的氧化物层的厚度或图案由测量的半导体晶片的翘曲或弯曲确定。 压缩氧化物层在半导体晶片的第二表面上引起偏移压缩力，以减少跨过半导体晶片的主表面的翘曲和弯曲。

公开(公告)号：WO2021155283A1

公开(公告)日：2021-08-05

申请号：PCT/US2021/015897

申请日：2021-01-29

Applicant: OSTENDO TECHNOLOGIES, INC.

Inventor： EL-GHOROURY, Hussein, S. ,  FAN, Qian ,  YADAVALLI, Kameshwar

IPC: F21S2/00 ,  H01L25/075 ,  H01L33/08 ,  H01L27/06

Abstract: A III-V light emitting device with pixels (mesa regions) specifically designed to enable lower cost through layer vias is disclosed for reduced cost of manufacture of the device. Reduction of cost of manufacture is achieved by having non-uniform width trench regions formed during pixel etch for the multi-pixel array part of the device. Through-layer vias are specifically formed in the wider part of the trench regions using cheaper lithography toolset enabled by the larger via critical dimension achievable in the wider part of the trench regions (as compared to narrow part of the trench regions). Larger via critical dimension enables improved electrical (and consequently optical) performance of the device due to better overlay control as well as lower via resistance.

公开(公告)号：WO2019241159A1

公开(公告)日：2019-12-19

申请号：PCT/US2019/036399

申请日：2019-06-10

Applicant: OSTENDO TECHNOLOGIES, INC.

Inventor： EL-GHOROURY, Hussein S. ,  YADAVALLI, Kameshwar ,  TEREN, Andrew ,  FAN, Qian

IPC: H01L33/00 ,  H01L33/46 ,  H01L33/50

Abstract: Solid state light emitting micropixels array structures having hydrogen barrier layers to minimize or eliminate undesirable passivation of doped GaN structures due to hydrogen diffusion.