公开(公告)号：WO2017106575A2

公开(公告)日：2017-06-22

申请号：PCT/US2016/067050

申请日：2016-12-15

Applicant: PDF SOLUTIONS, INC.

Inventor： LAM, Stephen ,  CIPLICKAS, Dennis ,  BROZEK, Tomasz ,  CHENG, Jeremy ,  COMENSOLI, Simone ,  DE, Indranil ,  DOONG, Kelvin ,  EISENMANN, Hans ,  FISCUS, Timothy ,  HAIGH, Jonathan ,  HESS, Christopher ,  KIBARIAN, John ,  LEE, Sherry ,  LIAO, Marci ,  LIN, Sheng-Che ,  MATSUHASHI, Hideki ,  MICHAELS, Kimon ,  O'SULLIVAN, Conor ,  RAUSCHER, Markus ,  ROVNER, Vyacheslav ,  STROJWAS, Andrzej ,  STROJWAS, Marcin ,  TAYLOR, Carl ,  VALLISHAYEE, Rakesh ,  WEILAND, Larg ,  YOKOYAMA, Nobuharu

CPC classification number: H01L22/26 ,  G01R31/2884 ,  G06F11/079 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/41725 ,  H01L29/45 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11885 ,  H01L2027/11887

Abstract: Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements ("NCEM"). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments ("DOEs"), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Abstract translation: 包含填充单元的晶片，芯片或管芯具有经配置以经由非接触式电气测量（“NCEM”）获得内嵌数据的结构。 这种NCEM使能的填充单元可以针对/暴露各种开路，短路，泄漏或过度电阻故障模式。 这样的晶片，芯片或管芯可以包括至少两个变体中的由多个NCEM使能的填充单元组成的实验设计（“DOE”），全部针对相同的故障模式。

公开(公告)号：WO2015192069A1

公开(公告)日：2015-12-17

申请号：PCT/US2015/035647

申请日：2015-06-12

Applicant: PDF SOLUTIONS, INC.

Inventor： DE, Indranil ,  CIPLICKAS, Dennis, J. ,  LAM, Stephen ,  HAIGH, Jonathan ,  ROVNER, Vyacheslav, V. ,  HESS, Christopher ,  BROZEK, Tomasz, W. ,  STROLJWAS, Andrezej, J. ,  DOONG, Kelvin ,  KIBARIAN, John, K. ,  LEE, Sherry, F. ,  MICHAELS, Kimon, W. ,  STROJWAS, Marcin, A. ,  O'SULLIVAN, Conor ,  JAIN, Mehul

IPC: H01L23/58

CPC classification number: H01L22/30 ,  H01L22/12 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0207

Abstract: Product ICs/wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill regions. Improved fabrication processes utilize data from such structure (s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis.

Abstract translation: 产品IC /晶片包括机会性放置在填充单元位置，抽头单元内，分解单元内，划线区域内和/或虚拟填充区域内的附加诊断，测试或监视结构。 改进的制造工艺利用晶片配置决定，返工决定，过程控制，产量学习或故障诊断中的这种结构的数据。