中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

65 records (took 0.024 seconds)

    INTERCONNECT CIRCUITS HAVING LOW THRESHOLD VOLTAGE P-CHANNEL TRANSISTORS FOR A PROGRAMMABLE INTEGRATED CIRCUIT
    3.
    发明申请
    INTERCONNECT CIRCUITS HAVING LOW THRESHOLD VOLTAGE P-CHANNEL TRANSISTORS FOR A PROGRAMMABLE INTEGRATED CIRCUIT 审中-公开
    具有可编程集成电路的低阈值电压P沟道晶体管的互连电路

    公开(公告)号：WO2016025261A1

    公开(公告)日：2016-02-18

    申请号：PCT/US2015/043755

    申请日：2015-08-05

    Applicant: XILINX, INC.

    Inventor： JAIN, Praful ,  HART, Michael, J.

    IPC: H03K19/177 ,  H03K19/173

    CPC classification number: H03K19/018571 ,  H01L27/11803 ,  H03K19/1737 ,  H03K19/17736 ,  H03K19/1776

    Abstract: An exemplary interconnect circuit (200) for a programmable integrated circuit (IC) (100) includes an input terminal (218-1 ) coupled to receive from a node (204) in the programmable IC, an output terminal (220) coupled to transmit towards another node (208) in the programmable IC, first and second control terminals (222-1, 222-2) coupled to receive from a memory cell (212) of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate (202-1 ) coupled between the input terminal and the output terminal and to the first and second control terminals. The CMOS pass-gate includes a P-channel transistor (Q2) configured with a low threshold voltage for a CMOS process used to fabricate the programmable IC. (Fig. 2).

    Abstract translation: 用于可编程集成电路（IC）（100）的示例性互连电路（200）包括耦合以从可编程IC中的节点（204）接收的输入端子（218-1），耦合到发射的输出端子（220） 朝向可编程IC中的另一节点（208），耦合到从可编程IC的存储单元（212）接收的第一和第二控制端（222-1,222-2）和互补金属氧化物半导体（CMOS）通路 - 门（202-1），其耦合在输入端子和输出端子之间以及耦合到第一和第二控制端子。 CMOS通道包括配置有用于制造可编程IC的CMOS工艺的低阈值电压的P沟道晶体管（Q2）。 （图2）。

    TRANSISTOR AND ITS METHOD OF MANUFACTURE
    4.
    发明申请
    TRANSISTOR AND ITS METHOD OF MANUFACTURE 审中-公开
    晶体管及其制造方法

    公开(公告)号：WO2013001282A2

    公开(公告)日：2013-01-03

    申请号：PCT/GB2012/051465

    申请日：2012-06-22

    Applicant: PRAGMATIC PRINTING LTD ,  PRICE, Richard ,  WHITE, Scott

    Inventor： PRICE, Richard ,  WHITE, Scott

    IPC: H01L29/66 ,  H01L27/12

    CPC classification number: H01L27/088 ,  G03F7/0002 ,  H01L21/0272 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/31144 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/11803 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L27/1292 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78666 ,  H01L29/78675 ,  H01L29/7869 ,  H01L51/0541

    Abstract: A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material;forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region;removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region;removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region;forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region.

    Abstract translation: 一种制造晶体管的方法，包括：提供衬底，由所述衬底支撑的半导体材料区域以及由所述半导体材料区域支撑的导电材料区域;形成至少一个层 在所述区域上形成抗蚀剂材料以在所述区域上形成抗蚀剂材料的覆盖物; 在所述抗蚀剂材料覆盖物的表面中形成凹陷，所述凹陷在所述导电材料区域的第一部分上延伸，所述第一部分将所述导电区域的第二部分与所述导电区域的第三部分分开;去除抗蚀剂材料 位于所述凹陷下方以形成窗口，穿过所述覆盖物，暴露所述导电区域的所述第一部分;移除所述第一部分以暴露所述半导体材料区域的连接部分，所述连接部分将所述第二部分连接到 所述导电区域的第三部分;在所述半导电材料区域的暴露部分上形成介电材料层; 以及沉积导电材料以在所述介电材料层上形成导电材料层，所述介电材料层将所述导电材料层与所述导电区域的第二和第三部分电隔离。

    半導体装置
    5.
    发明申请
    半導体装置 审中-公开
    半导体器件

    公开(公告)号：WO2011077940A1

    公开(公告)日：2011-06-30

    申请号：PCT/JP2010/071884

    申请日：2010-12-07

    Applicant: ミツミ電機株式会社 ,  笠原 正樹 ,  渡邊 敦 ,  亀田 朋潔

    Inventor： 笠原　正樹 ,  渡邊　敦 ,  亀田　朋潔

    IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L29/06 ,  H01L29/41 ,  H01L29/78

    CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/11803 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/41758 ,  H01L29/423 ,  H01L29/42368 ,  H01L29/7816

    Abstract: 　半導体基板の表面領域に形成され、対向して延在するソース領域及びドレイン領域と、前記半導体基板の表面上に形成され、前記ソース領域及びドレイン領域の間で前記ソース領域に沿って延在するゲートとを含む複数のトランジスタセルと、前記複数のトランジスタセルの周囲を囲み、前記半導体基板の基準電位を定める基板電極とを備えた半導体装置において、　前記半導体基板の表面領域の、前記ゲートに両側を挟まれた前記ドレイン領域の延在方向における端部と、前記基板電極との間の前記ドレイン領域の延長線上に、前記ドレイン領域と同電位の電流集中緩和電極が設けられたことを特徴とする半導体装置を提供する。

    Abstract translation: 公开了一种半导体器件，其设置有：多个晶体管单元，每个晶体管单元包括形成为彼此面对并在半导体衬底的表面区域上延伸的源极区域和漏极区域，以及栅极 形成在半导体衬底的表面上，以沿着源极区域和漏极区域之间的源极区域延伸; 以及包围晶体管单元周围的衬底电极，其指定半导体衬底的参考电位。 在漏极区域的延伸线上设置具有与漏极区域相等的电位的电流聚集缓和电极，在衬底电极和漏极区域的具有栅极的端部的两侧的表面区域上 半导体衬底。

    APPARATUS AND METHOD FOR FORMING COMPOUND INTEGRATED CIRCUITS
    7.
    发明申请
    APPARATUS AND METHOD FOR FORMING COMPOUND INTEGRATED CIRCUITS 审中-公开
    用于形成复合集成电路的装置和方法

    公开(公告)号：WO2005043601A3

    公开(公告)日：2005-12-01

    申请号：PCT/US2004036739

    申请日：2004-11-03

    Applicant: CHIPX INC ,  BATEMAN STEPHEN CHARLES ,  BAILEY DOUGLAS JOHN ,  COAKLEY DAVID JOHN

    Inventor： BATEMAN STEPHEN CHARLES ,  BAILEY DOUGLAS JOHN ,  COAKLEY DAVID JOHN

    IPC: G06F17/50 ,  H01L20060101

    CPC classification number: H01L27/0207 ,  H01L27/11803

    Abstract: The present invention provides for modularized circuits (500) and methods of manufacturing both modularized circuits ("master modules") (520, 522, 524, 526) and compound Ics (504). These master modules are designed to minimize waste and to evenly distribute power throughout its structure. Also, a number of master modules (520, 522, 524, 526) and a compound IC (504) composed of a group of these master modules are structured to minimize the effects of mechanically-induced stresses. In one embodiment, a substrate includes master modules (520, 522, 524, 526) distributed over a surface of the substrate, wherein each master module includes, for example, one or more logic circuits, a memory, an input interface and an output interface.

    Abstract translation: 本发明提供了模块化电路（500）和制造模块化电路（“主模块”）（520,522,524,526）和复合IC（504）的方法。 这些主模块旨在最大限度地减少浪费并在其整个结构中均匀分配电力。 此外，由一组这些主模块组成的多个主模块（520,522,524,526）和复合IC（504）被构造成使得机械感应应力的影响最小化。 在一个实施例中，衬底包括分布在衬底的表面上的主模块（520,522,524,526），其中每个主模块包括例如一个或多个逻辑电路，存储器，输入接口和输出 接口。

    IN SERVICE PROGRAMMABLE LOGIC ARRAYS WITH ULTRA THIN VERTICAL BODY TRANSISTORS
    8.
    发明申请
    IN SERVICE PROGRAMMABLE LOGIC ARRAYS WITH ULTRA THIN VERTICAL BODY TRANSISTORS 审中-公开
    服务可编程逻辑阵列与超薄立体体晶体管

    公开(公告)号：WO2002078186A1

    公开(公告)日：2002-10-03

    申请号：PCT/US2002/003243

    申请日：2002-02-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： FORBES, Leonard

    IPC: H03K19/177

    CPC classification number: H01L27/11803 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Structures and methods for in service programmable logic arrays with ultra thin vertical body transistors are provided. The in-service programmable logic array includes a first logic plane that receives a number of input signals. The first logic plane has a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A second logic plane has a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. Each of the logic cells includes a vertical pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. At least one single crystalline ultra thin vertical floating gate transistor that is disposed adjacent each vertical pillar. The single crystalline vertical floating gate transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A vertical floating gate opposes the ultra thin single crystalline vertical body region.

    Abstract translation: 提供了具有超薄垂直体晶体管的可编程逻辑阵列的结构和方法。 在役可编程逻辑阵列包括接收多个输入信号的第一逻辑平面。 第一逻辑平面具有互连以提供多个逻辑输出的以行和列布置的多个逻辑单元。 第二逻辑平面具有布置成行和列的多个逻辑单元，其接收第一逻辑平面的输出并互连以产生多个逻辑输出，使得在服务可编程逻辑阵列实现逻辑功能。 每个逻辑单元包括从半导体衬底向外延伸的垂直柱。 每个柱包括单晶第一接触层和由氧化物层分隔的第二接触层。 至少一个单晶超薄垂直浮栅晶体管，其设置在每个垂直柱附近。 单晶垂直浮栅晶体管包括耦合到第一接触层的超薄单晶垂直第一源/漏区，耦合到第二接触层的超薄单晶垂直第二源/漏区，以及超薄单晶 垂直体区域，其与氧化物层相对并耦合第一和第二源极/漏极区域。 垂直浮动门与超薄单晶垂直体区域相反。

    MASTER-SLICE SYSTEM SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGN METHOD THEREOF
    9.
    发明申请
    MASTER-SLICE SYSTEM SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGN METHOD THEREOF 审中-公开
    主系统半导体集成电路及其设计方法

    公开(公告)号：WO00005764A1

    公开(公告)日：2000-02-03

    申请号：PCT/JP1999/003955

    申请日：1999-07-23

    IPC: H01L27/02 ,  H01L27/10 ,  H01L27/108 ,  H01L27/118 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    CPC classification number: H01L27/11803 ,  H01L27/0207 ,  H01L27/11807 ,  Y10S257/909 ,  Y10S438/982

    Abstract: A method of arranging and wiring a master-slice system semiconductor integrated circuit which uses an automatic arranging/wiring device to arrange and wire first and second power source wirings (170, 171) crossing a plurality of basic cells (110) with respect to a master-slice (100) in which a plurality of basic cells (110) are arranged in a matrix form and a plurality of signal wirings for connecting the interiors of longitudinally arranged basic cells (110) and/or a plurality of basic cells (110) together, the method comprising a first step of registering the definitions of effective pin positions A1 to A14, B2 to B13, C1 to C14 in the automatic arranging/wiring device, a second step of registering a net list in the automatic arranging/wiring device and a third step of determining a pin arrangement and a wiring route according to the definitions of effective pin positions and net list information, wherein the registered effective pin positions exist on a lattice grid (120) and in and around areas between the first and second power source wirings (170, 171). Circuits wired based on this definition contact drains in and around the areas between the first and second power source wirings (170, 171) thus eliminating the possibility of signal wirings passing over the power source wirings.

    Abstract translation: 一种布置和布线主片系统半导体集成电路的方法，该主片系统半导体集成电路使用自动配置/布线装置来布置和布线与第一和第二电源布线相交的第一和第二电源布线（170,171） 其中以矩阵形式布置多个基本单元（110）的主切片（100）和用于连接纵向布置的基本单元（110）和/或多个基本单元（110）的内部的多个信号布线 ）一起，该方法包括在自动配置/接线装置中登记有效针脚位置A1至A14，B2至B13，C1至C14的定义的第一步骤，在自动布置/布线中注册网络列表的第二步骤 装置，以及根据有效引脚位置和网表信息的定义来确定引脚布置和布线路径的第三步骤，其中注册的有效引脚位置存在于网格（120）上，并且 围绕第一和第二电源布线（170,171）之间的区域。 基于该定义布线的电路接触在第一和第二电源布线（170,171）之间的区域内和周围，从而消除信号布线通过电源布线的可能性。

    METHOD FOR PRODUCING INTEGRATED CMOS CIRCUITS OR TRANSDUCERS CONTAINING CMOS CIRCUITS
    10.
    发明申请
    METHOD FOR PRODUCING INTEGRATED CMOS CIRCUITS OR TRANSDUCERS CONTAINING CMOS CIRCUITS 审中-公开
    用于生产包含CMOS电路的集成CMOS电路或传感器的方法

    公开(公告)号：WO1998011602A1

    公开(公告)日：1998-03-19

    申请号：PCT/EP1997004931

    申请日：1997-09-09

    Applicant: PHYSICAL ELECTRONICS LABORATORY ,  HAEBERLI, Andreas ,  HORNUNG, Mark ,  MUELLER, Thomas ,  SCHNEIDER, Michael

    Inventor： PHYSICAL ELECTRONICS LABORATORY

    IPC: H01L21/3063

    CPC classification number: B81C1/00246 ,  B81C2203/0728 ,  B81C2203/075 ,  C25F3/12 ,  G01L9/0042 ,  G01P15/0802 ,  H01L21/3063 ,  H01L27/11803 ,  H01L29/0657

    Abstract: According to the invention at least part of a CMOS circuit is decoupled from the bulk of the substrate by positioning this at least part of the CMOS circuit on a secondary substrate (2) with considerably less bulk than the original substrate (1) and by decoupling the secondary substrate (2) at least partly from the substrate (1). This is realised by a combination of multi-well technology and etching with electro-chemical etch stop either from the back or from the front of the wafer (e.g. anisotropic etching). A multi-well is a region consisting of a well diffusion (p- or n-doped) (2) which at least partially contains at least one further well diffusion (3), whereby the deepest well (2) or another well of the multi-well structure is designed to function as a secondary substrate.

    Abstract translation: 根据本发明，CMOS电路的至少一部分通过将该CMOS电路的至少一部分定位在次级衬底（2）上，与原始衬底（1）相比体积小得多，并通过去耦 所述第二衬底（2）至少部分地来自所述衬底（1）。 这通过多孔技术和来自晶片的背面或前面的电化学蚀刻停止（例如各向异性蚀刻）的蚀刻来实现。 多孔是由阱扩散（p-或n-掺杂）（2）组成的区域，其至少部分地包含至少一个另外的阱扩散（3），由此最深井（2）或另一井 多孔结构设计用作二次基板。

Patent Agency Ranking