公开(公告)号：WO2017204902A1

公开(公告)日：2017-11-30

申请号：PCT/US2017/025547

申请日：2017-03-31

Applicant: QUALCOMM INCORPORATED

Inventor： ZANUSO, Marco ,  ELBADRY, Mohammad ,  HUNG, Tsai-Pi ,  SRIDHARA, Ravi ,  GATTA, Francesco ,  ZHUANG, Jingcheng

IPC: H03L7/14

CPC classification number: H04L7/033 ,  H03L7/14 ,  H03L7/143 ,  H03L7/1976 ,  H03L2207/08 ,  H04L5/14 ,  H04L69/28 ,  H04W84/042

Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

Abstract translation: 相位锁定环（PLL）内的相位不连续性缓解实现提高了无线电接入技术的吞吐量。 在断开PLL的一些器件（如本地振荡器（LO）分频器）时，通过保持PLL的相位来改善吞吐量。 在一个实例中，当PLL断电时，PLL的一个或多个部分的Δ-Σ调制器以PLL的参考时钟为时钟。 当第一个锁相环打开时，此实现可保持相位连续性。

公开(公告)号：WO2015183588A1

公开(公告)日：2015-12-03

申请号：PCT/US2015/030948

申请日：2015-05-15

Applicant: QUALCOMM INCORPORATED

Inventor： LO, Yung-Chung ,  ZHANG, Gang ,  HAN, Yiping ,  BOSSU, Frederic ,  HUNG, Tsai-Pi ,  CHANG, Jae-Hong

IPC: G05F1/575

CPC classification number: H02M3/156 ,  G05F1/575 ,  H02M1/00 ,  H02M2001/0077

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator.

Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置可以是调节器电路。 调节器电路包括第一电压调节器，用于调节到第一电压调节器的第一输入电压，第一电压调节器包括P型金属氧化物半导体（PMOS）和第二电压调节器，以将第二输入电压调节到 第二电压调节器，第二电压调节器包括N型金属氧化物半导体（NMOS）。 在一方面，第一电压调节器耦合到第二电压调节器。

公开(公告)号：WO2017053120A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/051358

申请日：2016-09-12

Applicant: QUALCOMM INCORPORATED

Inventor： JIN, Zhang ,  YANG, Tao ,  HUNG, Tsai-Pi ,  FARAZIAN, Mohammad

IPC: H01L23/522

CPC classification number: H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H03H7/004

Abstract: Metal-oxide-metal (MOM) type capacitors include a first terminal configured to receive a first voltage, the first terminal being formed on a first dielectric layer; a first set of fingers formed on the first dielectric layer, the first set of fingers being coupled to the first terminal via a conductive trace formed on a second dielectric layer; a second terminal configured to receive second voltage, the second terminal being formed on the first dielectric layer; and a second set of fingers formed on the first dielectric layer, the second set of fingers being coupled to the second terminal, wherein the fingers of the second set are interspersed with the fingers of the first set.

Abstract translation: 金属氧化物金属（MOM）型电容器包括被配置为接收第一电压的第一端子，第一端子形成在第一介电层上; 形成在所述第一介电层上的第一组指状物，所述第一组指状物经由形成在第二介电层上的导电迹线耦合到所述第一端子; 第二端子，被配置为接收第二电压，所述第二端子形成在所述第一电介质层上; 以及形成在所述第一介电层上的第二组指状物，所述第二组指状物联接到所述第二终端，其中所述第二组的指状物与所述第一组的手指分散。

公开(公告)号：WO2015183428A1

公开(公告)日：2015-12-03

申请号：PCT/US2015/026922

申请日：2015-04-21

Applicant: QUALCOMM INCORPORATED

Inventor： BOSSU, Frederic ,  YOUSSEF, Ahmed Abdel Monem ,  HUNG, Tsai-Pi ,  GUDEM, Prasad Srinivasa Siva

IPC: H01L27/02 ,  H02H9/04

CPC classification number: G05F1/46 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0266 ,  H02H9/045 ,  H02H9/046

Abstract: An apparatus includes an input/output (I/O) pin and an electrostatic discharge device. The electrostatic discharge device is coupled to the I/O pin and to a voltage regulator.

Abstract translation: 一种装置包括输入/​​输出（I / O）引脚和静电放电装置。 静电放电装置耦合到I / O引脚和电压调节器。

公开(公告)号：WO2017189160A1

公开(公告)日：2017-11-02

申请号：PCT/US2017/025171

申请日：2017-03-30

Applicant: QUALCOMM INCORPORATED

Inventor： ZANUSO, Marco ,  MARUCCI, Giovanni ,  HUNG, Tsai-Pi ,  GATTA, Francesco ,  SUN, Bo

IPC: H04B1/713 ,  H03L7/197 ,  H03L7/08

CPC classification number: H04L7/0331 ,  H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H03L7/113 ,  H03L7/1974 ,  H03L7/1976 ,  H03L2207/06 ,  H04B1/40 ,  H04B1/713 ,  H04B2201/71353 ,  H04W72/0453

Abstract: A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.

Abstract translation: 锁相环（PLL）电路中的快速跳频实现在很短的时间内实现了PLL锁定到新的频率。 在一个瞬间，收发器处的频率分配被改变。 作为响应，基于改变的频率分配，本地振荡器频率跳跃到新的中心频率。 跳到新的中心频率是基于锁相环的两点调制。

公开(公告)号：WO2012078922A3

公开(公告)日：2012-06-14

申请号：PCT/US2011/064023

申请日：2011-12-08

Applicant: QUALCOMM INCORPORATED ,  NARATHONG, Chiewcharn ,  PARK, Jong Min ,  HUNG, Tsai-Pi

Inventor： NARATHONG, Chiewcharn ,  PARK, Jong Min ,  HUNG, Tsai-Pi

IPC: H03M1/66 ,  H03L7/099

Abstract: A circuit includes a digital-to-analog converter with non-uniform resolution for converting a digital signal into an analog signal. The digital-to-analog converter includes high-resolution circuitry, reduced-resolution circuitry coupled to the high-resolution circuitry and a switch coupled to the high-resolution circuitry and to the reduced-resolution circuitry. The switch couples one of the high-resolution circuitry and the reduced-resolution circuitry to an output node. The circuit also includes a decoder coupled to the switch. The decoder receives the digital signal to control the switch.