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    PHASE CONTINUITY TECHNIQUE FOR FREQUENCY SYNTHESIS
    1.
    发明申请
    PHASE CONTINUITY TECHNIQUE FOR FREQUENCY SYNTHESIS 审中-公开
    用于频率综合的相位连续技术

    公开(公告)号：WO2017204902A1

    公开(公告)日：2017-11-30

    申请号：PCT/US2017/025547

    申请日：2017-03-31

    Applicant: QUALCOMM INCORPORATED

    Inventor： ZANUSO, Marco ,  ELBADRY, Mohammad ,  HUNG, Tsai-Pi ,  SRIDHARA, Ravi ,  GATTA, Francesco ,  ZHUANG, Jingcheng

    IPC: H03L7/14

    CPC classification number: H04L7/033 ,  H03L7/14 ,  H03L7/143 ,  H03L7/1976 ,  H03L2207/08 ,  H04L5/14 ,  H04L69/28 ,  H04W84/042

    Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

    Abstract translation: 相位锁定环（PLL）内的相位不连续性缓解实现提高了无线电接入技术的吞吐量。 在断开PLL的一些器件（如本地振荡器（LO）分频器）时，通过保持PLL的相位来改善吞吐量。 在一个实例中，当PLL断电时，PLL的一个或多个部分的Δ-Σ调制器以PLL的参考时钟为时钟。 当第一个锁相环打开时，此实现可保持相位连续性。

    CHARGE PUMP WITH VOLTAGE TRACKING
    2.
    发明申请
    CHARGE PUMP WITH VOLTAGE TRACKING 审中-公开

    公开(公告)号：WO2022241356A1

    公开(公告)日：2022-11-17

    申请号：PCT/US2022/071654

    申请日：2022-04-10

    Applicant: QUALCOMM INCORPORATED

    Inventor： PAI, Hung-Chuan ,  ZANUSO, Marco

    IPC: H03L7/089 ,  H03L7/093 ,  H03L2207/06 ,  H03L7/0891 ,  H03L7/0893

    Abstract: An apparatus is disclosed for a charge pump with voltage tracking. In an example aspect, the apparatus includes a locked loop having a charge pump, a filter, a second switch, and a buffer. The charge pump includes a first current source, a second current source, and a first switch coupled between the first current source and the second current source. The filter is coupled to the charge pump between the first switch and the second current source. The second switch is coupled to the charge pump between the first current source and the first switch. The buffer is coupled between the filter and the second switch, with the buffer comprising a voltage buffer.

    PHASE-LOCKED LOOP (PLL) WITH MULTIPLE ERROR DETERMINERS
    3.
    发明申请
    PHASE-LOCKED LOOP (PLL) WITH MULTIPLE ERROR DETERMINERS 审中-公开

    公开(公告)号：WO2022046339A1

    公开(公告)日：2022-03-03

    申请号：PCT/US2021/043311

    申请日：2021-07-27

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHAO, Yue ,  ZANUSO, Marco ,  RANGARAJAN, Rajagopalan ,  TANG, Yiwu

    IPC: H03L7/087 ,  H03L7/081 ,  H03L7/197 ,  H03L7/089 ,  H03L7/183

    Abstract: An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and multiple error determiners. The loop filter includes a filter input node and a filter output node. The VCO includes a VCO input node and a VCO output node. The VCO input node is coupled to the filter output node. The frequency divider includes a divider input node and multiple divider output nodes. The divider input node is coupled to the VCO output node. The multiple error determiners are coupled between the multiple divider output nodes and the filter input node.

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