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    APPARATUS AND METHOD FOR IN SITU ANALOG SIGNAL DIAGNOSTIC AND DEBUGGING WITH CALIBRATED ANALOG-TO-DIGITAL CONVERTER
    4.
    发明申请
    APPARATUS AND METHOD FOR IN SITU ANALOG SIGNAL DIAGNOSTIC AND DEBUGGING WITH CALIBRATED ANALOG-TO-DIGITAL CONVERTER 审中-公开
    用于原位模拟信号诊断和调试以及校准的模拟数字转换器的设备和方法

    公开(公告)号：WO2018044519A1

    公开(公告)日：2018-03-08

    申请号：PCT/US2017/046111

    申请日：2017-08-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： SONG, Deqiang ,  KONG, Xiaohua ,  PANDITA, Bupesh ,  GAO, Zhuo

    IPC: G01R31/316 ,  H03M1/10 ,  H03M1/12 ,  G01R31/3167

    CPC classification number: H03M1/06 ,  G01R31/2884 ,  G01R31/3167 ,  H03M1/1009 ,  H03M1/12

    Abstract: An integrated circuit (IC) chip includes an on-chip analog signal monitoring circuit for monitoring a set of analog signals generated by one or more mixed signal cores within the IC chip, converting the analog signals into digital signals, storing the digital signals in an on-chip memory, and providing the digital signals to a test equipment upon request. The analog signal monitoring signal includes an on-chip reference generator for generating precise voltages and/or currents, a switching network for routing a selected reference signal to an analog-to-digital converter (ADC) for calibration purpose and for routing a selected analog signal from one of the mixed signal cores to the ADC for digitizing purposes. The IC chip further includes an on-chip memory for storing the digitized analog signals for subsequent accessing by a test equipment for analysis. The IC chip includes a digital analog test point (ATP) for outputting the digitized analog signals.

    Abstract translation: 集成电路（IC）芯片包括片上模拟信号监视电路，用于监视由IC芯片内的一个或多个混合信号内核产生的一组模拟信号，将模拟信号转换为数字信号 信号，将数字信号存储在片上存储器中，并根据请求将数字信号提供给测试设备。 模拟信号监视信号包括用于产生精确电压和/或电流的片上参考发生器，用于将选定参考信号路由到模数转换器（ADC）以用于校准目的并用于路由选定模拟信号的开关网络 信号从一个混合信号内核传送到ADC以进行数字化。 IC芯片还包括片上存储器，用于存储数字化模拟信号，以供测试设备随后访问以供分析。 IC芯片包括一个用于输出数字化模拟信号的数字模拟测试点（ATP）。

    APPARATUS AND METHOD FOR COMBINING CURRENTS FROM PASSIVE EQUALIZER IN SENSE AMPLIFIER
    5.
    发明申请
    APPARATUS AND METHOD FOR COMBINING CURRENTS FROM PASSIVE EQUALIZER IN SENSE AMPLIFIER 审中-公开
    用于在感测放大器中组合来自被动均衡器的电流的装置和方法

    公开(公告)号：WO2017065909A1

    公开(公告)日：2017-04-20

    申请号：PCT/US2016/051359

    申请日：2016-09-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： HAILU, Eskinder ,  COHEN, Hanan ,  PANDITA, Bupesh

    IPC: H03F3/45 ,  H04B3/04

    CPC classification number: H04L25/03885 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1084 ,  H03F3/24 ,  H03F3/45183 ,  H03F2203/45352 ,  H03F2203/45544 ,  H03F2203/45591 ,  H03F2203/45644 ,  H03G5/005 ,  H03G5/24 ,  H04B3/18

    Abstract: An apparatus configured to apply equalization to an input data signal and detect data based on the equalized data signal. The apparatus includes a passive equalizer comprising a first signal path configured to generate a first signal based on an input signal, and a second signal path configured to generate a second signal by filtering the input signal. The apparatus further includes a sense amplifier having an input circuit configured to generate a third signal related to a combination of the first and second signals, and a data detection circuit configured to generate data based on the third signal. The data detection circuit may be configured as a strong-arm latch. The third signal may be a differential current signal including positive and negative current components. The strong-arm latch generating data based on whether the positive current component is greater than the negative current component.

    Abstract translation: 被配置为将均衡应用于输入数据信号并且基于均衡的数据信号来检测数据的装置。 该装置包括无源均衡器，该无源均衡器包括被配置为基于输入信号生成第一信号的第一信号路径和被配置为通过对输入信号进行滤波生成第二信号的第二信号路径。 该装置还包括读出放大器，该读出放大器具有被配置为生成与第一信号和第二信号的组合相关的第三信号的输入电路以及被配置为基于第三信号生成数据的数据检测电路。 数据检测电路可以被配置为强臂锁存器。 第三信号可以是包括正电流分量和负电流分量的差分电流信号。 强臂锁存器根据正电流分量是否大于负电流分量生成数据。

    PHASE LOCKED LOOP (PLL) ARCHITECTURE
    6.
    发明申请
    PHASE LOCKED LOOP (PLL) ARCHITECTURE 审中-公开
    相位锁定环路（PLL）架构

    公开(公告)号：WO2016144486A1

    公开(公告)日：2016-09-15

    申请号：PCT/US2016/017847

    申请日：2016-02-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： ARCUDIA, Kenneth Luis ,  SHAFER, Jeffrey Andrew ,  PANDITA, Bupesh

    IPC: H03L7/091 ,  H03L7/093

    CPC classification number: H04L7/0332 ,  H03B5/1212 ,  H03B5/1228 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0025 ,  H04L7/041

    Abstract: In one embodiment, a phase locked loop (PLL) comprises a voltage-controlled oscillator (VCO), a frequency divider configured to frequency divide an output signal of the VCO to produce a feedback signal, and a phase detection circuit configured to detect a phase difference between a reference signal and the feedback signal, and to generate an output signal based on the detected phase difference. The PLL also comprises a proportional circuit configured to generate a control voltage based on the output signal of the phase detection circuit, wherein the control voltage tunes a first capacitance of the VCO to provide phase correction. The PLL further comprises an integration circuit configured to convert the control voltage into a digital signal, to integrate the digital signal, and to tune a second capacitance of the VCO based on the integrated digital signal to provide frequency tracking.

    Abstract translation: 在一个实施例中，锁相环（PLL）包括压控振荡器（VCO），分频器，被配置为频率分频VCO的输出信号以产生反馈信号;以及相位检测电路，被配置为检测相位 参考信号和反馈信号之间的差异，并且基于检测到的相位差产生输出信号。 PLL还包括比例电路，其被配置为基于相位检测电路的输出信号产生控制电压，其中控制电压调谐VCO的第一电容以提供相位校正。 PLL还包括集成电路，其被配置为将控制电压转换为数字信号，以集成数字信号，并且基于积分数字信号来调谐VCO的第二电容以提供频率跟踪。

    DELAY LOCKED LOOP (DLL) EMPLOYING PULSE TO DIGITAL CONVERTER (PDC) FOR CALIBRATION
    7.
    发明申请
    DELAY LOCKED LOOP (DLL) EMPLOYING PULSE TO DIGITAL CONVERTER (PDC) FOR CALIBRATION 审中-公开

    公开(公告)号：WO2019009997A1

    公开(公告)日：2019-01-10

    申请号：PCT/US2018/038130

    申请日：2018-06-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： HAILU, Eskinder ,  PANDITA, Bupesh

    IPC: H03L7/081 ,  H03L7/085

    Abstract: Aspects of the disclosure are directed to generating a quadrature clock signal from an in-phase clock signal. In accordance with one aspect, a delay locked loop (DLL), including a first pulse to digital converter (PDC) to generate a first pulse width measurement, wherein the first pulse width measurement includes a first sign and a first magnitude; a second pulse to digital converter (PDC) to generate a second pulse width measurement, wherein the second pulse width measurement includes a second sign and a second magnitude; a digital loop filter coupled to the first PDC and the second PDC, the digital loop filter to generate a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and a first delay generation block to generate a quadrature clock signal based on the filtered comparison output and an in-phase clock signal.

    PULSE TO DIGITAL CONVERTER
    8.
    发明申请
    PULSE TO DIGITAL CONVERTER 审中-公开

    公开(公告)号：WO2019009996A1

    公开(公告)日：2019-01-10

    申请号：PCT/US2018/038129

    申请日：2018-06-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： HAILU, Eskinder ,  PANDITA, Bupesh

    IPC: H03M1/50 ,  H03M1/14 ,  G04F10/00 ,  H03M1/20

    Abstract: Aspects of the disclosure are directed to a pulse to digital converter. In accordance with one aspect, the pulse to digital converter includes an input to receive an input pulse signal; a fractional element, coupled to the input, wherein the fractional element generates a fractional pulse width measurement of the input pulse signal; and an integral element, coupled to the input, wherein the integral element generates an integral pulse width measurement of the input pulse signal, and wherein the fractional pulse width measurement and the integral pulse width measurement are concatenated as an output signal.

    A GATE BOOSTED LOW DROP REGULATOR
    9.
    发明申请
    A GATE BOOSTED LOW DROP REGULATOR 审中-公开
    门升降低降压调节器

    公开(公告)号：WO2017172343A1

    公开(公告)日：2017-10-05

    申请号：PCT/US2017/022195

    申请日：2017-03-13

    Applicant: QUALCOMM INCORPORATED

    Inventor： GAO, Zhuo ,  PANDITA, Bupesh

    IPC: G05F1/575

    Abstract: In certain aspects, a voltage regulator includes a pass transistor having a drain coupled to an input of the voltage regulator, a source coupled to an output of the voltage regulator, and a gate. The voltage regulator also includes an amplifier having a first input coupled to a reference voltage, a second input coupled to a feedback voltage, and an output, wherein the feedback voltage is approximately equal to or proportional to a voltage at the output of the voltage regulator. The voltage regulator further includes a voltage booster having an input coupled to the output of the amplifier and an output coupled to the gate of the pass transistor, wherein the voltage booster is configured to boost a voltage at the input of the voltage booster to generate a boosted voltage, and to output the boosted voltage at the output of the voltage booster.

    Abstract translation: 在某些方面，电压调节器包括具有耦合到电压调节器的输入的漏极，耦合到电压调节器的输出的源极和栅极的传输晶体管。 电压调节器还包括具有耦合到参考电压的第一输入，耦合到反馈电压的第二输入和输出的放大器，其中反馈电压近似等于或成比例于电压调节器的输出处的电压 。 该电压调节器还包括电压升压器，该电压升压器具有耦合到放大器的输出的输入和耦合到传输晶体管的栅极的输出，其中升压器配置为升高电压升压器的输入处的电压以产生 升压电压，并在升压器的输出端输出升压电压。

    NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE
    10.
    发明申请
    NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE 审中-公开
    新的相位锁相环（PLL）架构

    公开(公告)号：WO2017027132A1

    公开(公告)日：2017-02-16

    申请号：PCT/US2016/041380

    申请日：2016-07-07

    Applicant: QUALCOMM INCORPORATED

    Inventor： PANDITA, Bupesh ,  COHEN, Hanan ,  HAILU, Eskinder ,  ARCUDIA, Kenneth Luis

    IPC: H03L7/18 ,  H03L7/197

    CPC classification number: H03K21/10 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03L7/1976

    Abstract: In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

    Abstract translation: 在一个实施例中，用于分频的方法包括将模数信号向上传播到一级级联分频器级从最后一级分频级到第一级除法器级，并且对于每个分频级，产生相应的本地 当模数信号传播到分频器级之后的负载信号。 该方法还包括对于每个分频器级，基于相应的本地负载信号将一个或多个相应的控制位输入到分频器级，所述一个或多个相应的控制位设置分频器级的分频器值。

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