公开(公告)号：WO2018071874A2

公开(公告)日：2018-04-19

申请号：PCT/US2017/056681

申请日：2017-10-13

Applicant: SANMINA CORPORATION

Inventor： IKETANI, Shinichi ,  DOUGLAS WARD, Thomas

IPC: H05K3/46

Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core, A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A. conductive material is then plated to an inner surface of the second hole.

Abstract translation: 公开了一种使用双钻孔和电镀方法制造印刷电路板通孔的方法。 在核心中钻出第一孔，第一孔具有第一直径。 第一孔填充和/或电镀导电材料。 可以在芯的一个或两个导电层上形成电路图案。然后可以形成包括多个芯的多层结构，所述多个芯还包括预钻孔和电镀通孔，其中至少一些预钻孔和电镀 通孔与第一孔对齐。 然后在第一孔和对齐的预钻孔和镀孔内钻出第二孔，第二孔具有第二直径，其中第二直径小于第一直径。 A.然后将导电材料镀到第二孔的内表面上。

公开(公告)号：WO2018175660A1

公开(公告)日：2018-09-27

申请号：PCT/US2018/023660

申请日：2018-03-21

Applicant: SANMINA CORPORATION

Inventor： IKETANI, Shinichi

IPC: H05K3/42 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K3/0047 ,  H05K3/02 ,  H05K3/06 ,  H05K3/4069 ,  H05K3/423 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2203/0207 ,  H05K2203/061 ,  H05K2203/0723

Abstract: A multilayer PCB having may include a first sub-composite core having a first core structure sandwiched between a first conductive layer and a second conductive layer, the first core structure including one or more dielectric and conductive layers. A first via hole extends at least partially through the first core structure, wherein an inner surface of the first via hole is plated with a conductive material along a first via segment electrically coupling the first conductive layer to an internal layer or trace within the first core structure. A second via segment extending between the second conductive layer and the internal layer or trace is devoid of the conductive material such that the first via hole is substantially stub free. A first dielectric layer is coupled to the second conductive layer. A second sub-composite core coupled to the first dielectric layer.

公开(公告)号：WO2015004541A3

公开(公告)日：2015-01-15

申请号：PCT/IB2014/002315

申请日：2014-06-23

Applicant: SANMINA CORPORATION

Inventor： IKETANI, Shinichi ,  KERSTEN, Dale

IPC: H05K3/10 ,  H05K3/46

Abstract: A core or sub-composite structure is provided including a dielectric layer between a first conductive film and a second conductive film. The first conductive film may include a first peelable/removable cover layer formed on or coupled to a first conductive layer. The second conductive film may include a second peelable/removable cover layer formed on or coupled to a second conductive layer.

公开(公告)号：WO2018071874A3

公开(公告)日：2018-04-19

申请号：PCT/US2017/056681

申请日：2017-10-13

Applicant: SANMINA CORPORATION

Inventor： IKETANI, Shinichi ,  DOUGLAS WARD, Thomas

IPC: H05K3/46 ,  H05K3/42

Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core, A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A. conductive material is then plated to an inner surface of the second hole.

公开(公告)号：WO2016106428A1

公开(公告)日：2016-06-30

申请号：PCT/US2015/067736

申请日：2015-12-28

Applicant: SANMINA CORPORATION

Inventor： IKETANI, Shinichi ,  KERSTEN, Dale

IPC: H05K3/40 ,  H05K1/11

CPC classification number: H05K3/429 ,  H05K3/0035 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/421 ,  H05K2203/0207 ,  H05K2203/0713 ,  H05K2203/1476

Abstract: A method for forming a hole plug in a laminate structure is provided. A laminate structure, is formed, including at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. An unpierced or blind hole is formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the hole having a hole depth to hole diameter aspect ratio of less than ten (10) to one (1). In yet another example, the hole aspect ratio may be less than one (1) to one (1). Via fill ink may then be deposited in the hole. The via fill ink is then dried and/or cured to form a hole plug.

Abstract translation: 提供了一种形成层压结构中的孔塞的方法。 形成层压体结构，在电介质层的第一侧上至少包括介电层和第一导电箔。 在层叠结构中形成未钝化或盲孔，从电介质层的第二侧朝向第一导电箔延伸，并且至少部分地穿过电介质层，孔的孔深孔直径纵横比小于10（ 10）到一（1）。 在另一个例子中，孔长宽比可以小于一（1）至1（1）。 然后，通过填充油墨可以沉积在孔中。 然后将通孔填充油墨干燥和/或固化以形成孔塞。

公开(公告)号：WO2015112758A1

公开(公告)日：2015-07-30

申请号：PCT/US2015/012523

申请日：2015-01-22

Applicant: SANMINA CORPORATION

Inventor： THOMAS, Douglas, Ward ,  IKETANI, Shinichi ,  KERSTEN, Dale

IPC: H05K3/40 ,  H05K3/42

CPC classification number: H05K3/429 ,  H05K1/0216 ,  H05K3/24 ,  H05K2201/09845 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/072 ,  H05K2203/0723

Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.

Abstract translation: 印刷电路板（PCB）技术领域本发明涉及印刷电路板（PCB），更具体地涉及在印刷电路板（PCB）中形成高纵横比通孔和高精度短截线的方法。 高精度残留物去除过程可用于去除长桩和短桩。 在该方法中，使用不同直径的钻头从印刷电路板的上表面和/或下表面钻出不同直径和深度的多个孔。

公开(公告)号：WO2015095401A1

公开(公告)日：2015-06-25

申请号：PCT/US2014/070966

申请日：2014-12-17

Applicant: SANMINA CORPORATION

Inventor： IKETANI, Shinichi ,  KERSTEN, Dale

IPC: H05K3/46

CPC classification number: H05K3/429 ,  H05K2201/09645 ,  H05K2203/0713 ,  Y10T29/49165

Abstract: Novel methods for forming a printed circuit board (PCB) having one or more segmented vias are provided, including improved methods of removing the catalyst after the plating process when forming a segmented via in the PCB. After the electroless plating, excess catalyst on the surface of the plating resist is removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, electrolytic plating is then applied to the through holes and the outer layer circuit or signal traces are formed. That is, the etching of paths on the conductive foils/layers of the core structure.

Abstract translation: 提供了一种用于形成具有一个或多个分段通孔的印刷电路板（PCB）的新方法，包括在电镀工艺之后形成分段通孔在PCB中去除催化剂的改进方法。 在化学镀后，使用催化剂去除剂，例如至少包括亚硝酸根或亚硝酸根离子和卤素离子的酸性溶液除去电镀抗蚀剂表面上的过量催化剂，或者催化剂去除剂可以是电镀抗蚀剂的蚀刻剂， 例如包括氧，氮，氩和四氟甲烷中的至少一种的碱金属高锰酸盐化合物溶液或等离子体气体，或这些气体中的至少两种的混合物。 除去过量的催化剂后，对通孔施加电解电镀，形成外层电路或信号迹线。 也就是说，蚀刻在芯结构的导电箔/层上的路径。