公开(公告)号：WO2013133919A1

公开(公告)日：2013-09-12

申请号：PCT/US2013/024288

申请日：2013-02-01

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： TOREN, Willem-jan ,  LIU, Xian ,  METZGER-BRUECKL, Gerhard ,  DO, Nhan ,  WEGE, Stephan ,  MIRIDI, Nadia ,  SU, Chien-sheng ,  BERNARDI, Cecile ,  CUEVAS, Liz ,  GUYOT, Florence ,  CHEN, Yueh-hsin ,  OM'MANI, Henry ,  TADAYONI, Mandana

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11568

Abstract: A stack gate structure for use in a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions. Stack gate structures are formed over active regions, and each includes a first insulating material is between each stack gate structure in the second direction perpendicular to the first direction, a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, a first portion of a control gate over the third insulating material, a second portion of the control gate is over the top surface of the first portion of the control gate and over the top surface of the first insulating material adjacent thereto and extending in the second direction and a fourth insulating material is over the second portion of the control gate.

Abstract translation: 用于非易失性存储器阵列的堆叠栅极结构具有半导体衬底，该半导体衬底具有多个基本上平行的间隔开的有效区域。 堆叠栅极结构形成在有源区上，并且每个包括在垂直于第一方向的第二方向上的每个堆叠栅极结构之间的第一绝缘材料，在有源区上方的第二绝缘材料，位于第二绝缘材料上方的电荷保持栅极 在所述电荷保持栅极上方的第三绝缘材料，所述第三绝缘材料上的控制栅极的第一部分，所述控制栅极的第二部分在所述控制栅极的第一部分的顶表面之上，并且超过所述控制栅极的顶表面 与其相邻并在第二方向上延伸的第一绝缘材料和第四绝缘材料在控制栅极的第二部分之上。

公开(公告)号：WO2015002923A1

公开(公告)日：2015-01-08

申请号：PCT/US2014/045003

申请日：2014-07-01

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-sheng ,  YANG, Jeng-wei ,  CHEN, Yueh-hsin

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823425 ,  H01L29/1608 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

Abstract translation: 一种具有一对导电浮动栅极的存储器件，所述导电浮动栅极具有彼此面对的内侧壁，并且设置在第一导电类型的衬底上并与其绝缘。 一对间隔开的导电控制栅极，每个导电控制栅极设置在浮动栅极中的一个上并与之隔绝，并且每个包括彼此面对的内侧壁。 一对绝缘材料的第一间隔物，沿着控制栅极内侧壁和浮动栅极延伸。 浮动门内侧壁与第一间隔件的侧表面对准。 绝缘材料的一对第二间隔物各自沿着第一间隔件中的一个并且沿着浮动栅极内侧壁中的一个延伸。 形成在衬底中的沟槽，其具有与第二间隔物的侧表面对齐的侧壁。 设置在沟槽中的硅碳。 材料注入到硅碳中，形成具有第二导电类型的第一区域。

公开(公告)号：WO2014143408A1

公开(公告)日：2014-09-18

申请号：PCT/US2014/011934

申请日：2014-01-16

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-sheng ,  YANG, Jeng-wei ,  TADAYONI, Mandana ,  CHEN, Yueh-hsin

IPC: H01L21/336

CPC classification number: H01L29/66477 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of forming an MOS transistor by forming a poly gate over and insulated from a substrate, forming a layer of protective insulation material on the poly gate, and then performing a first implant of dopant material into portions of the substrate adjacent the poly gate, wherein the layer of protective insulation material and the poly gate block most or all of the first implant from reaching a portion of the substrate underneath the poly gate. One or more spacers are then formed adjacent the poly gate, followed by a second implant of dopant material into portions of the substrate adjacent to the one or more spacers.

Abstract translation: 一种形成MOS晶体管的方法，该方法是在多晶硅栅极上形成保护绝缘材料层，然后在邻近多晶硅栅极的基板的第一部分中进行第一次掺杂， 其中所述保护绝缘材料层和所述多晶硅栅极阻挡所述第一注入的大部分或全部到达所述多晶硅栅极下方的所述衬底的一部分。 然后在多晶硅栅极附近形成一个或多个间隔物，随后将掺杂剂材料第二次注入到与该一个或多个间隔物相邻的衬底的部分中。