公开(公告)号：WO2022060489A1

公开(公告)日：2022-03-24

申请号：PCT/US2021/045170

申请日：2021-08-09

Applicant: TELEDYNE SCIENTIFIC & IMAGING, LLC

Inventor： SHINOHARA, Keisuke ,  KING, Casey ,  REGAN, Eric ,  URTEAGA, Miguel

IPC: H01L29/778 ,  H01L29/872 ,  H01L29/41 ,  H01L29/423 ,  H01L29/06 ,  H01L29/20

Abstract: Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source (304) and drain (306) electrodes channel, a gate electrode structure (307), and a dielectric layer (312). The gate electrode structure includes an electrode (308) in contact with the channel and a lateral field plate (332) adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode, cathodes and lateral field plates located between the anode and the cathodes.

公开(公告)号：WO2021262421A1

公开(公告)日：2021-12-30

申请号：PCT/US2021/035914

申请日：2021-06-04

Applicant: TELEDYNE SCIENTIFIC & IMAGING, LLC

Inventor： URTEAGA, Miguel ,  CARTER, Andy

IPC: H01L29/08 ,  H01L21/683 ,  H01L23/36 ,  H01L29/40 ,  H01L29/417 ,  H01L21/331 ,  H01L29/737 ,  H01L29/45 ,  H01L29/47 ,  H01L21/3212 ,  H01L21/6835 ,  H01L21/8252 ,  H01L2221/68363 ,  H01L29/0821 ,  H01L29/401 ,  H01L29/41708 ,  H01L29/475 ,  H01L29/66318 ,  H01L29/7371

Abstract: A method of forming a bipolar transistor with a vertical collector contact requires providing a transistor comprising a plurality of epitaxial semiconductor layers on a first substrate, and providing a host substrate. A metal collector contact is patterned on the top surface of the host substrate, and the plurality of epitaxial semiconductor layers is transferred from the first substrate onto the metal collector contact on the host substrate. The first substrate is suitably the growth substrate for the plurality of epitaxial semiconductor layers. The host substrate preferably has a higher thermal conductivity than does the first substrate, which improves the heat dissipation characteristics of the transistor and allows it to operate at higher power densities. A plurality of transistors may be transferred onto a common host substrate to form a multi-finger transistor.

公开(公告)号：WO2019010313A1

公开(公告)日：2019-01-10

申请号：PCT/US2018/040931

申请日：2018-07-05

Applicant: TELEDYNE SCIENTIFIC & IMAGING, LLC

Inventor： SHINOHARA, Keisuke ,  URTEAGA, Miguel ,  KING, Casey ,  CARTER, Andy

IPC: H01L29/778

Abstract: A FET with a buried gate structure. The FET' s gate electrode comprises a plurality of buried gate structures, the tops of which extend above the substrate's top surface and the bottoms of which are buried to a depth at least equal to that of the bottom of the channel layer, or the 2DEG plane within a channel layer for a HEMT, such that the buried gate structures contact the channel layer only from its sides. A head portion above and not in contact with the substrate's top surface contacts the tops of and interconnects all of the buried gate structures. Drain current is controlled by channel width modulation by lateral gating of the channel layer by the buried gates structures. The FET may include at least one field plate which comprises a slit structure in which the field plate is divided into segments.