公开(公告)号：WO2011010286A3

公开(公告)日：2011-11-24

申请号：PCT/IB2010053317

申请日：2010-07-21

Applicant: UNIV RAMOT ,  SHARON ERAN ,  ALROD IDAN ,  LITSYN SIMON

Inventor： SHARON ERAN ,  ALROD IDAN ,  LITSYN SIMON

IPC: H03M13/00 ,  H03M13/25 ,  H04L1/00

CPC classification number: H03M13/1185 ,  H03M13/1111 ,  H03M13/616 ,  H03M13/6362 ,  H03M13/6393 ,  H04L1/0013 ,  H04L1/0052 ,  H04L1/0057 ,  H04L1/0069

Abstract: k input bits are encoded according to a code with which is associated a m x n=m+k parity check matrix H. The resulting codeword is punctured, with n' bits. The punctured codeword is exported to a corrupting medium such as a communication channel or a memory. A representation of the punctured codeword is imported from the corrupting medium and is decoded using a matrix H' that is smaller than H. For example, H' is m'=m~(n-n ') x n' and is derived by merging selected rows of H. Alternatively, H has at most m rows and fewer than n columns but more than n' columns. Alternatively, H has fewer than m'=m-(n-n') rows and fewer than n' columns.

Abstract translation: k个输入比特根据与m×n = m + k个奇偶校验矩阵H相关联的代码进行编码。所产生的码字用n'比特打孔。 删截的码字被导出到诸如通信信道或存储器之类的破坏媒体。 删截码字的表示从破坏介质导入并使用小于H的矩阵H'解码。例如，H'是m'= m〜（nn'）×n'并且通过合并选择的行 的H.或者，H具有至多m行，少于n列但多于n'列。 或者，H具有少于m'= m-（n-n'）行且少于n'列。

公开(公告)号：WO2009156935A1

公开(公告)日：2009-12-30

申请号：PCT/IB2009052662

申请日：2009-06-22

Applicant: UNIV RAMOT ,  SHARON ERAN ,  LITSYN SIMON ,  ALROD IDAN

Inventor： SHARON ERAN ,  LITSYN SIMON ,  ALROD IDAN

IPC: H03M13/11

CPC classification number: H03M13/1137 ,  H03M13/1114 ,  H03M13/114 ,  H03M13/3753 ,  H03M13/618 ,  H03M13/6362 ,  H03M13/658

Abstract: To decode a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, estimates of the codeword bits are updated by exchanging messages between JV bit nodes and N-K check nodes of a graph in a plurality of iterations. In each of one or more of the iterations, some or all values associated with the bit nodes, and/or some or all values associated with check nodes, and/or some or all messages are modified in a manner that depends explicitly on the ordinality of the iteration and is independent of any other iteration. Alternatively, the modifications are according to respective locally heteromorphic rules.

Abstract translation: 为了将从信道导入的表示解码为将K个信息比特编码为N> K个码字比特的码字，通过在图中的JV比特节点和NK校验节点之间交换消息来更新码字比特的估计， 迭代。 在一个或多个迭代中的每一个中，与位节点相关联的一些或所有值，和/或与校验节点相关联的一些或所有值和/或某些或所有消息以明确依赖于序数的方式被修改 的迭代，并且独立于任何其他迭代。 或者，修改根据各自的本地异形规则。

公开(公告)号：WO2008142683A3

公开(公告)日：2009-02-12

申请号：PCT/IL2008000685

申请日：2008-05-20

Applicant: UNIV RAMOT ,  SHARON ERAN ,  LITSYN SIMON ,  ALROD IDAN

Inventor： SHARON ERAN ,  LITSYN SIMON ,  ALROD IDAN

IPC: H03M13/11

CPC classification number: H03M13/114 ,  H03M13/6505

Abstract: To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N-K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes.

Abstract translation: 为了将编码K个信息比特的码字的表示解码为N个K个码字比特，消息在其中E个边缘连接比特节点和校验节点的图的N个比特节点和N-K个校验节点之间进行交换。 当消息被交换时，存储少于E个消息，和/或存储少于N个码字比特的软估计。 在一些实施例中，消息仅在子图中以及子图和一个或多个外部校验节点之间交换。 当消息被交换时，最大数量的存储消息是具有最多边缘的子图中的边数加上将子图连接到外部校验节点的边数，和/或最大 存储的软估计数是具有最多位节点的子图中的比特节点的数量。

公开(公告)号：WO2008081426B1

公开(公告)日：2008-08-14

申请号：PCT/IL2007001567

申请日：2007-12-19

Applicant: UNIV RAMOT ,  ALROD IDAN ,  SHARON ERAN ,  LITSYN SIMON

Inventor： ALROD IDAN ,  SHARON ERAN ,  LITSYN SIMON

IPC: G06F11/10 ,  G11C7/10 ,  G11C11/56

CPC classification number: G11C11/5628 ,  G06F11/1072 ,  G11C7/1006 ,  G11C29/00

Abstract: Memory circuitry, or a memory device controller, or a host of a memory device, store an input string of M N-tuples of bits by selecting a substitution transformation in accordance with the input string and by applying the transformation to the input string to provide a transformed string of M N-tuples of bits. M or more memory cells are programmed to represent the transformed string and preferably also to represent a key of the transformation. Alternatively, the circuitry selectively programs each of M or more cells to a respective one of 2N states. The circuitry or the controller selects a mapping that maps the binary numbers in [0,2N-1] into respective states in accordance with the input string and the circuitry uses the mapping to program M cells to represent the input string. Preferably, a key of the mapping is stored in the memory in association with the M cells.

Abstract translation: 存储器电路或存储器件控制器或存储器件的主机通过根据输入字符串选择替换变换并通过将变换应用于输入字符串来存储M个N元组的输入串，以提供 一个M位元组的变换字符串。 M个或更多个存储器单元被编程以表示变换的字符串，并且优选地也表示转换的关键字。 或者，电路选择性地将M个或更多个单元中的每一个编程为2N个状态中的相应的一个。 电路或控制器根据输入字符串选择将[0,2N-1]中的二进制数映射到各自状态的映射，并且电路使用映射来编程M个单元来表示输入字符串。 优选地，映射的密钥与M个单元相关联地存储在存储器中。

公开(公告)号：WO2007102141A3

公开(公告)日：2009-04-09

申请号：PCT/IL2006001251

申请日：2006-10-30

Applicant: UNIV RAMOT ,  LITSYN SIMON ,  SHARON ERAN ,  ALROD IDAN

Inventor： LITSYN SIMON ,  SHARON ERAN ,  ALROD IDAN

IPC: G06F12/00

CPC classification number: G11C16/10 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/34 ,  G11C29/42 ,  G11C2211/5641

Abstract: To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to one or may be an "into" generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.

Abstract translation: 为了存储多个输入位，这些位被映射到一个或多个存储器单元的相应的编程状态，并且单元被编程为相应的编程状态。 映射可以是多对一的，或者可以是“到”广义灰色映射。 读取单元以提供被转换成多个输出位的读取状态值，例如通过最大似然解码或通过将读取状态值映射到多个软比特中，然后解码软比特 。

公开(公告)号：WO2007043042A3

公开(公告)日：2008-12-31

申请号：PCT/IL2006001159

申请日：2006-10-04

Applicant: UNIV RAMOT ,  LITSYN SIMON ,  ALROD IDAN ,  SHARON ERAN ,  MURIN MARK ,  LASSER MENACHEM

Inventor： LITSYN SIMON ,  ALROD IDAN ,  SHARON ERAN ,  MURIN MARK ,  LASSER MENACHEM

IPC: G11C29/00

CPC classification number: G06F11/1072

Abstract: A plurality of logical pages is stored in a MBC flash memory (42) along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory (42), the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices (54, 56, 5S), the controllers of such memory devices (54, 56, 58), and also computer-readable storage media bearing computer-readable code for implementing the methods.

Abstract translation: 多个逻辑页面与相应的ECC位一起存储在MBC闪速存储器（42）中，其中至少一个MBC单元存储来自多于一个逻辑页面的位，并且至少一个ECC位应用于两个 或更多的逻辑页面。 当从存储器（42）读取页面时，读取的数据位使用被读取的ECC位进行校正。 或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。 当读取联合码字时，从读取的码字中恢复逻辑比特。 本发明的范围还包括对应的存储设备（54,56,5S），这些存储设备（54,56,58）的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

公开(公告)号：WO2007135657A3

公开(公告)日：2009-04-09

申请号：PCT/IL2006001248

申请日：2006-10-30

Applicant: UNIV RAMOT ,  SHARON ERAN ,  ALROD IDAN ,  LITSYN SIMON

Inventor： SHARON ERAN ,  ALROD IDAN ,  LITSYN SIMON

IPC: H03M13/00

CPC classification number: H03M13/3738 ,  H03M13/3707 ,  H03M13/6502 ,  H03M13/6511

Abstract: A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably, applying the first decoder consumes less power and is faster than applying the second decoder. Data are ported by encoding the data as a codeword, exporting the codeword to a corrupting medium, importing a representation of the codeword, and applying a first decoder to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword.

Abstract translation: 通过将码字的第一解码器应用于码字的表示来解码码字的表示。 如果应用第一解码器不能解码码字的表示，则码字的第二解码器被应用于码字的表示。 优选地，应用第一解码器消耗较少的功率并且比应用第二解码器更快。 数据通过将数据编码为码字来移植，将码字导出到破坏性介质，导入码字的表示，以及将第一解码器应用于码字的表示。 如果应用第一解码器不能解码码字的表示，则码字的第二解码器被应用于码字的表示。

公开(公告)号：WO2008075351A2

公开(公告)日：2008-06-26

申请号：PCT/IL2007001565

申请日：2007-12-19

Applicant: UNIV RAMOT ,  ALROD IDAN ,  SHARON ERAN ,  LITSYN SIMON ,  LASSER MENAHEM

Inventor： ALROD IDAN ,  SHARON ERAN ,  LITSYN SIMON ,  LASSER MENAHEM

IPC: G11C16/26

CPC classification number: G11C11/5642 ,  G06F11/1068 ,  G06F11/1072 ,  G11C16/26 ,  G11C2211/5634

Abstract: To read one or more flash memory cells, the threshold voltage of each cell is compared to at least one integral reference voltage and to at least one fractional reference voltage. Based on the comparisons, a respective estimate probability measure of each bit of an original bit pattern of each cell is calculated. This provides a plurality of estimated probability measures. Based at least in part on at least two of the estimated probability measures, respective original bit patterns of the cells are estimated. Preferably, the estimated probability measures are initial probability measures that are transformed to final probability measures under the constraint that the bit pattern(s) (collectively) is/are a member of a candidate set, e.g. a set of codewords.

Abstract translation: 为了读取一个或多个闪存单元，将每个单元的阈值电压与至少一个积分参考电压和至少一个分数参考电压进行比较。 基于比较，计算每个单元的原始位模式的每个位的相应估计概率度量。 这提供了多个估计的概率测量。 至少部分地基于估计的概率度量中的至少两个，估计单元的各个原始位模式。 优选地，所估计的概率测量值是初始概率测量值，其在约束下（一个或多个）位模式（总称）是候选集的成员，例如， 一组码字。

公开(公告)号：WO2007046084A2

公开(公告)日：2007-04-26

申请号：PCT/IL2006001175

申请日：2006-10-15

Applicant: UNIV RAMOT ,  LITSYN SIMON ,  ALROD IDAN ,  SHARON ERAN ,  MURIN MARK ,  LASSER MENACHEM

Inventor： LITSYN SIMON ,  ALROD IDAN ,  SHARON ERAN ,  MURIN MARK ,  LASSER MENACHEM

IPC: G06F19/00

CPC classification number: G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C2029/0409

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract translation: 根据系统或非系统ECC存储在多比特单元存储器的单元中的数据根据​​估计的概率被读取和校正（系统ECC）或恢复（非系统ECC） 更多的读取位是错误的。 在本发明的一种方法中，估计是先验的。 在本发明的另一种方法中，估计仅基于包括读位的重要性或位页的读位的方面。 在本发明的第三种方法中，估计仅基于读位的值。 并不是所有的估计是相等的。

公开(公告)号：WO2011010286A2

公开(公告)日：2011-01-27

申请号：PCT/IB2010053317

申请日：2010-07-21

Applicant: UNIV RAMOT ,  SHARON ERAN ,  ALROD IDAN ,  LITSYN SIMON

Inventor： SHARON ERAN ,  ALROD IDAN ,  LITSYN SIMON

CPC classification number: H03M13/1185 ,  H03M13/1111 ,  H03M13/616 ,  H03M13/6362 ,  H03M13/6393 ,  H04L1/0013 ,  H04L1/0052 ,  H04L1/0057 ,  H04L1/0069

Abstract: k input bits are encoded according to a code with which is associated a m x n=m+k parity check matrix H. The resulting codeword is punctured, with n' bits. The punctured codeword is exported to a corrupting medium such as a communication channel or a memory. A representation of the punctured codeword is imported from the corrupting medium and is decoded using a matrix H' that is smaller than H. For example, H' is m'=m~(n-n ') x n' and is derived by merging selected rows of H. Alternatively, H has at most m rows and fewer than n columns but more than n' columns. Alternatively, H has fewer than m'=m-(n-n') rows and fewer than n' columns.

Abstract translation: k个输入比特根据与m×n = m + k个奇偶校验矩阵H相关联的代码进行编码。所得到的码字以n'比特被打孔。 穿孔码字被导出到诸如通信信道或存储器的破坏介质。 穿孔码字的表示是从破坏介质中导入的，并且使用小于H的矩阵H'进行解码。例如，H'是m'= m〜（nn'）xn'，并且通过合并所选择的行而导出 或者，H具有至多m行且少于n列但大于n'列。 或者，H具有少于m'= m-（n-n'）行且小于n'列。