公开(公告)号：WO2016186930A1

公开(公告)日：2016-11-24

申请号：PCT/US2016/031919

申请日：2016-05-11

Applicant: XILINX, INC.

Inventor： MCLEOD, Scott, D. ,  IM, Hsung, Jai ,  CHEN, Stanley, Y.

IPC: G01R31/3185 ,  H03K5/00

CPC classification number: G01R31/041 ,  G01R31/2884 ,  G01R31/318572 ,  H03K3/012 ,  H03K3/3568 ,  H03K19/017527 ,  H03K19/018514 ,  H04L25/0272

Abstract: In one example, a driver circuit includes a differential transistor pair (504) configured to be biased by a current source (502) and including a differential input (516) and a differential output (512). The driver circuit further includes a resistor pair (506) coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements (510) having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.

Abstract translation: 在一个示例中，驱动器电路包括被配置为由电流源（502）偏置并包括差分输入（516）和差分输出（512）的差分晶体管对（504）。 驱动器电路还包括耦合在节点对和差分输出之间的电阻器对（506），耦合在电压源和节点对之间的晶体管对以及耦合在节点对之间的桥式晶体管。 驱动器电路还包括一对三态电路元件（510），其具有相应的一对输入端口，相应的一对控制端口和相应的一对输出端口。 输出端口对分别耦合到节点对。 该对控制端口耦合到包括晶体管对的每个栅极和桥式晶体管的栅极的公共节点。

公开(公告)号：WO2019177945A1

公开(公告)日：2019-09-19

申请号：PCT/US2019/021574

申请日：2019-03-11

Applicant: XILINX, INC.

Inventor： ZHUANG, Yi ,  LIN, Winson ,  NAMKOONG, Jinyung ,  IM, Hsung, Jai ,  CHEN, Stanley, Y.

IPC: H03L7/08 ,  H03L7/081 ,  H04L7/033

Abstract: A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler (202) configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit (204) configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator (206) configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.