公开(公告)号：WO2023086282A1

公开(公告)日：2023-05-19

申请号：PCT/US2022/049072

申请日：2022-11-07

Applicant: WOLFSPEED, INC.

Inventor： MCPHERSON, Brice ,  SINGH, Shashwat ,  SCHUPBACH, Roberto M.

IPC: H01L23/31 ,  H01L23/495

Abstract: A power module is provided with a substrate, power devices, and a housing. The power devices are mounted on device pads of the substrate and arranged to provide a power circuit having a first input, a second input, and at least one output. First and second power terminals provide first and second inputs for the power circuit. At least one output power terminal provides at least one output. The housing encompasses the substrate, the power devices, and portions of the first and second input power terminals as well as the at least one output power terminal. The first and second input power terminals extend out of a first side of the housing, and the at least one output power terminal extends out of a second side of the housing, the first side being opposite the second side.

公开(公告)号：WO2023034773A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/075631

申请日：2022-08-30

Applicant: WOLFSPEED, INC.

Inventor： RADULESCU, Fabian ,  NOORI, Basim ,  SHEPPARD, Scott ,  LIM, Kwangmo Chris

IPC: H01L23/04 ,  H01L23/057 ,  H01L23/36 ,  H01L23/482 ,  H01L29/41 ,  H01L23/485 ,  H01L23/66 ,  H01L23/08 ,  H01L23/31

Abstract: A radio frequency ("RF") transistor amplifier die includes a semiconductor layer structure having a plurality of transistor cells, and an insulating layer on a surface of the semiconductor layer structure. Conductive pillar structures protrude from the insulating layer opposite the surface of the semiconductor layer structure, and are configured to provide input signal, output signal, or ground connections to the transistor cells. The ground connections are arranged between the input and/or output signal connections to the transistor cells. Related devices and packages are also discussed.

公开(公告)号：WO2023009405A1

公开(公告)日：2023-02-02

申请号：PCT/US2022/038121

申请日：2022-07-25

Applicant: WOLFSPEED, INC.

Inventor： HARDIMAN, Chris ,  NAMISHIA, Daniel ,  BOTHE, Kyle ,  KEENAN, Elizabeth

IPC: H01L21/56 ,  H01L23/31 ,  H01L29/66

Abstract: A transistor device includes a substrate, a semiconductor structure on the substrate, a metallization layer comprising a non-planar surface on a surface of the semiconductor structure, a non-planar encapsulation layer on the non-planar surface of the metallization layer, the non-planar encapsulation layer comprising a non-planar encapsulant surface that is opposite the non-planar surface, and a self-planarizing encapsulation layer on the non-planar encapsulation layer and comprising a planarized surface that is opposite the non-planar encapsulant surface.

公开(公告)号：WO2022245417A1

公开(公告)日：2022-11-24

申请号：PCT/US2022/018489

申请日：2022-03-02

Applicant: WOLFSPEED, INC.

Inventor： SMITH, JR., Thomas J. ,  SRIRAM, Saptharishi

IPC: H01L21/82 ,  H01L27/02 ,  H01L27/085

Abstract: An apparatus for reducing lag includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a gate control circuit configured to control a gate voltage of the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and an area between the gate and the drain.

公开(公告)号：WO2022178023A1

公开(公告)日：2022-08-25

申请号：PCT/US2022/016644

申请日：2022-02-16

Applicant: WOLFSPEED, INC.

Inventor： LICHTENWALNER, Daniel Jenner ,  VAN BRUNT, Edward Robert ,  HARRINGTON, III, Thomas E. ,  SABRI, Shadi ,  HULL, Brett ,  MCPHERSON, Brice ,  MCPHERSON, Joe W.

IPC: H01L23/482 ,  H01L23/00 ,  H01L29/423 ,  H01L29/78

Abstract: Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.

公开(公告)号：WO2021225860A1

公开(公告)日：2021-11-11

申请号：PCT/US2021/029848

申请日：2021-04-29

Applicant: WOLFSPEED, INC.

Inventor： FLOWERS, Mitch ,  COHEN, Erwin ,  KOMPOSCH, Alexander ,  WALL, Larry Christopher

IPC: H01L21/77 ,  H01L21/70 ,  H01L21/71

Abstract: A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.

公开(公告)号：WO2023069601A1

公开(公告)日：2023-04-27

申请号：PCT/US2022/047253

申请日：2022-10-20

Applicant: WOLFSPEED, INC.

Inventor： BOTHE, Kyle ,  JONES, Evan

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/45 ,  H01L29/20

Abstract: A transistor includes a semiconductor layer and a channel region. The transistor further includes a first doped contact region in the semiconductor layer and adjacent the channel region. The transistor further includes a first ohmic contact including an interface region comprising a first interface length between the first ohmic contact and the first doped contact region larger than a length of the interface region. The interface including at least one indentation, increasing a periphery of the interface, thereby improving a total contact resistance of the transistor.

公开(公告)号：WO2022256196A1

公开(公告)日：2022-12-08

申请号：PCT/US2022/030619

申请日：2022-05-24

Applicant: WOLFSPEED, INC.

Inventor： LEE, Kyoung-Keun ,  ETTER, Daniel ,  RADULESCU, Fabian ,  SHEPPARD, Scott ,  NAMISHIA, Daniel

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/053 ,  H01L23/482

Abstract: A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes a plurality of sublayers that are stacked on the semiconductor body. Each of the sublayers comprises a respective stress in one or more directions, where the respective stresses of at least two of the sublayers are different. The sublayers may include a first stressor sublayer comprising first stress, and a second stressor sublayer comprising a second stress that at least partially compensates for the first stress in the one or more directions. Related devices and methods of fabrication are also discussed.

公开(公告)号：WO2022226142A1

公开(公告)日：2022-10-27

申请号：PCT/US2022/025680

申请日：2022-04-21

Applicant: WOLFSPEED, INC.

Inventor： MCPHERSON, Brice ,  PASSMORE, Brandon ,  SCHUPBACH, Roberto, M. ,  STABACH-SMITH, Jennifer

IPC: H01L23/495 ,  H01L23/053 ,  H01L23/31 ,  H02M7/00 ,  H02M7/5387

Abstract: The present disclosure describes a power module having a substrate, first and second pluralities of vertical power devices, and first and second terminal assemblies. The substrate has a top surface with a first trace and a second trace. The first plurality of vertical power devices and the second plurality of vertical power devices are electrically coupled to form part of a power circuit. The first plurality of vertical power devices is electrically and mechanically directly coupled between the first trace and a bottom of a first elongated bar of the first terminal assembly. The second plurality of vertical power devices are electrically and mechanically directly coupled between the second trace and a bottom of a second elongated bar of the second terminal assembly.

公开(公告)号：WO2022125495A1

公开(公告)日：2022-06-16

申请号：PCT/US2021/062121

申请日：2021-12-07

Applicant: WOLFSPEED, INC. [US]/[US]

Inventor： RICHMOND, James ,  VAN BRUNT, Edward, Robert

IPC: H01L21/66 ,  H01L29/16 ,  H01L29/78

Abstract: Semiconductor devices, and in particular semiconductor devices for improved resistance measurements and related methods are disclosed. Contact structures for semiconductor devices are disclosed that provide access to resistance measurements with reduced influence of testing-related resistances, thereby improving testing accuracy, particularly for semiconductor devices with low on-resistance ratings. A semiconductor device may include an active region and an inactive region that is arranged along a perimeter of the active region. The semiconductor device may be arranged with a topside contact to provide access for resistance measurements, for example Kelvin-sensing resistance measurements. Related methods include performing resistance measurements from a topside of the semiconductor device, even when the active region of the semiconductor device forms a vertical contact structure.