公开(公告)号：WO2008112888A1

公开(公告)日：2008-09-18

申请号：PCT/US2008/056848

申请日：2008-03-13

Applicant: UNIVERSITY OF HOUSTON ,  WOLFE, John C. ,  RUCHHOEFT, Paul

Inventor： WOLFE, John C. ,  RUCHHOEFT, Paul

IPC: G03F1/00

CPC classification number: B01D67/0032 ,  B01D67/0034 ,  B01D71/48 ,  B01D2323/42 ,  B01D2325/028 ,  G03F7/12 ,  G03F7/2037 ,  H01J37/3056 ,  H01J2237/3174 ,  H01J2237/31755 ,  H01J2237/31788

Abstract: Various embodiments disclose devices and methods for fabricating microporous particulate filters with regularly space pores wherein sheet membrane substrates are exposed to energetic particle radiation through a mask and the damaged regions removed in a suitable developer. The required depth of field is achieved by using energetic particles to minimize diffraction and an energetic particle source with suitably small diameter.

Abstract translation: 各种实施方案公开了用于制造具有规则空间孔的微孔微粒过滤器的装置和方法，其中片膜衬底通过掩模暴露于高能粒子辐射，并且在合适的显影剂中去除损伤区域。 所需的景深是通过使用能量粒子来最小化衍射和具有适当小直径的能量粒子源实现的。

公开(公告)号：WO2007064956A1

公开(公告)日：2007-06-07

申请号：PCT/US2006/046125

申请日：2006-11-30

Applicant: CADENCE DESIGN SYSTEMS, INC. ,  LAPANIK, Dmitri ,  MATSUSHITA, Shohei ,  MITSUHASHI, Takashi ,  WU, Zhigang

Inventor： LAPANIK, Dmitri ,  MATSUSHITA, Shohei ,  MITSUHASHI, Takashi ,  WU, Zhigang

IPC: H01J37/302 ,  H01J37/317

CPC classification number: G03F1/16 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/78 ,  G06F17/50 ,  H01J37/3026 ,  H01J37/3174 ,  H01J2237/31762 ,  H01J2237/31788

Abstract: A system and method for improved electron beam writing that is capable of taking design intent, equipment capability and design requirements into consideration. The system and method determines an optimal writing pattern based, at least in part, on the received information.

Abstract translation: 一种能够考虑设计意图，设备能力和设计要求的改进电子束写入的系统和方法。 该系统和方法至少部分地基于所接收的信息来确定最佳写入模式。

公开(公告)号：WO2006054086A2

公开(公告)日：2006-05-26

申请号：PCT/GB2005004435

申请日：2005-11-17

Applicant: NFAB LTD ,  EASTHAM DEREK ANTONY

Inventor： EASTHAM DEREK ANTONY

IPC: H01J37/317

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01J37/3177 ,  H01J2237/20228 ,  H01J2237/3175 ,  H01J2237/31788

Abstract: A mask suitable for use with a particle beam source such as ion or electron source for forming features and structures and writing on surfaces of materials. The mask comprising an aperture plate, having a plurality of apertures, and focussing means disposed to underlie the aperture plate. The plurality of apertures forming an array whereby each plate aperture is adapted to receive a portion of a particle beam incident on the aperture plate. Each portion of particle beam then passes through focusing means through which the portion of beam is focussed onto the surface. The mask thereby forming a plurality of high resolution simultaneously operable focussed particle beams.

Abstract translation: 适合与粒子束源（例如离子或电子源）一起使用以形成特征和结构并在材料表面上书写的掩模。 所述掩模包括具有多个孔的孔板，以及设置在所述孔板下面的聚焦装置。 所述多个孔形成阵列，由此每个板孔适于接收入射在孔板上的一部分粒子束。 然后，粒子束的每个部分通过聚焦装置，通过该聚焦装置将光束的该部分聚焦在该表面上。 该掩模由此形成多个高分辨率的可同时操作的聚焦粒子束。

公开(公告)号：WO1990011614A1

公开(公告)日：1990-10-04

申请号：PCT/JP1990000388

申请日：1990-03-23

Applicant: HITACHI, LTD. ,  WAKABAYASHI, Hiroaki ,  NAKAYAMA, Yoshinori ,  MURAI, Fumio ,  OKAZAKI, Shinji

Inventor： HITACHI, LTD.

IPC: H01L21/027

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01J37/3174 ,  H01J2237/31776 ,  H01J2237/31788

Abstract: A method of exposure to an electron beam and related devices in a process for producing a very large scale integrated circuit. Exposure has been so far effected in divided steps. In this invention, use is made of an aperture diaphragm having the shape of pattern within a predetermined area and the arrangement thereof formed as a single crystal silicon thin-film pattern, and the exposure is effected in one step for one predetermined area. According to the invention, the exposure is completed in about several hundred times fewer steps than in the prior art, contributing to strikingly increasing the throughout. Further, there is substantially no difference in the number of exposure steps irrespective of whether the pattern is complex or not, and each process can be carried out requiring nearly the same time.

Abstract translation: 在制造大规模集成电路的过程中暴露于电子束和相关器件的方法。 曝光已经在分开的步骤中受到影响。 在本发明中，使用具有规定区域内的图案形状的孔径光阑，其形成为单晶硅薄膜图案，并且在一个步骤中对一个预定区域进行曝光。 根据本发明，曝光以比现有技术大约几百倍的步骤完成，有助于显着增加。 此外，无论图案是否复杂，曝光步骤数量基本上没有差异，并且每个处理可以进行几乎相同的时间。

公开(公告)号：WO1981000930A1

公开(公告)日：1981-04-02

申请号：PCT/US1980001176

申请日：1980-09-12

Applicant: HUGHES AIRCRAFT CO

Inventor： HUGHES AIRCRAFT CO ,  SELIGER R

IPC: H01J37/317

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01J37/3174 ,  H01J2237/30438 ,  H01J2237/31755 ,  H01J2237/31767 ,  H01J2237/31788

Abstract: A high-resolution, high-throughput ion beam lithography process and apparatus is used in the fabrication of semiconductor integrated circuits and devices. Lateral wafer distortions which occur in wafer workpieces create the problem of accurate alignment of the ion beam with the wafer. Furthermore, it is difficult to produce a collimated ion beam of sufficient diameter for a large area target. These problems are overcome by exposing selected segments of the wafer to a projected ion beam pattern in a step-and-repeat manner until the entire target is exposed, thereby optimizing the resolution, throughput, yield and cost of the process. First there is provided: a target (12) having predetermined segments (14) defined thereon; a mask (16) placed in proximity to the target (12), to define the patterned ion beam; a collimated ion beam which is projected through the mask (16) to form the patterned ion beam; and a means (22, 34, 35) for aligning the mask (16) and a selected segment (14) of the target (12). The size of the pattern area of the mask (16) is approximately equal to the size of one of the predetermined segments (14) of the target (12). Next, the mask (16) is aligned with a first selected segment (14) of the target (12) and this first segment (14) is exposed to the patterned ion beam, formed by projecting the collimated ion beam through the mask (16). Then, the mask (16) is aligned with a second selected segment of the target (12) and this second segment is exposed to the patterned ion beam.

公开(公告)号：WO2007096505A2

公开(公告)日：2007-08-30

申请号：PCT/FR2007000287

申请日：2007-02-16

Applicant: CENTRE NAT RECH SCIENT ,  GIERAK JACQUES

Inventor： GIERAK JACQUES

CPC classification number: H01J37/20 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G01Q80/00 ,  H01J37/3174 ,  H01J2237/20228 ,  H01J2237/20235 ,  H01J2237/20264 ,  H01J2237/244 ,  H01J2237/31732 ,  H01J2237/31737 ,  H01J2237/31755 ,  H01J2237/31788

Abstract: Nanofabrication installation comprising: a specimen holder, for holding a specimen; a mask, having a through-opening between the upper and lower faces of the mask, for letting charged particles through onto the specimen holder; a near-field detection device for detecting a relative position between the mask (8) and the specimen holder (3); and a displacement device for generating a relative movement between the mask (8) and the specimen holder (3) independently of the relative position between the source (1) and the mask (8), the mask including at least a first electrode in the through-opening (10).

Abstract translation: 纳米制造设备包括：用于保持样本的样本保持器; 一个掩模，在掩模的上下面之间有一个通孔，用于使带电粒子通过样品架; 近场检测装置，用于检测所述掩模（8）和所述样品架（3）之间的相对位置; 以及位移装置，用于独立于所述源（1）和所述掩模（8）之间的相对位置而在所述掩模（8）和所述样本保持器（3）之间产生相对运动，所述掩模包括所述掩模 （10）。

公开(公告)号：WO2005048327A1

公开(公告)日：2005-05-26

申请号：PCT/JP2004/017043

申请日：2004-11-10

Applicant: 株式会社ニコン ,  平柳 徳行

Inventor： 平柳 徳行

IPC: H01L21/027

CPC classification number: H01J37/3175 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/70466 ,  H01J2237/31788

Abstract: 　まず、マスク１０上のメカニカルストライプＩをウェハ２３上に露光転写する。このとき、コンプリメンタリパターン領域Ａ 1 は、ウェハ２３上のメカニカルストライプの像Ｉ´の右端Ａ 1 'に転写される。次に、マスク１０上のメカニカルストライプIIをウェハ２３上に露光転写する。この際、マスクステージ及びウェハステージを走査して、メカニカルストライプの像II'がＩ'と幅ｄだけ重なり合うようにすることにより、コンプリメンタリパターン領域Ａ 2 の像Ａ 2 'が、ウェハ２３上でＡ 1 'と重ね合わされる。これにより、分割すべきパターンが偏在する場合において、マスクのコストを抑え、スループットを高めるように改良した露光方法を実現することができる。

Abstract translation: 首先，将掩模（10）上的机械条纹I曝光转印到晶片（23）上。 这里，互补图案区域A1被转印到晶片（23）上的机械条纹图像I'的右端A1'。 接下来，掩模（10）上的机械条纹II被曝光转印到晶片（23）上。 这里，通过扫描掩模台和晶片台，机械条纹的图像II'仅以宽度d重叠在I'上，使得互补图案区域A2的图像A2'叠加在A1' 在晶片（23）上。 因此，当要划分的图案集中在某个位置时，可以实现能够抑制掩模成本并提高生产量的曝光方法。

公开(公告)号：WO1987005438A1

公开(公告)日：1987-09-11

申请号：PCT/US1987000106

申请日：1987-01-27

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： HUGHES AIRCRAFT COMPANY ,  McKENNA, Charles, M. ,  WOOD, James, E. ,  BARTELT, John, L. ,  OLNEY, Ross, D. ,  WARD, J., William ,  SLAYMAN, Charles, W.

IPC: H01J37/317

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01J37/3174 ,  H01J2237/055 ,  H01J2237/1516 ,  H01J2237/303 ,  H01J2237/31755 ,  H01J2237/31788

Abstract: A masked ion beam lithography (MIBL) system and method which is considerably more compact and economical than prior ion implantation devices. An H+ ion beam is extracted from a source (4) in the form of an angularly expanding beam, and is transmitted through two lenses (14 and 16) that sequentially accelerate the ions to energies in the range of 200-300 keV. The first lens (14) focuses the beam so that it emerges from a crossover point with an amplified angular divergence at least three times the divergence of the initial beam, thereby considerably reducing the necessary column length. The second lens (16) collimates the beam so that it can be directed onto a mask (32) to expose resist on an underlying semiconductor substrate (36). A series of extraction electrodes (58 and 60) are used to provide an initial point source beam with a desired angular expansion, and a specially designed sector magnet (8) is positioned between the extraction mechanism (6) and the first lens (14) to remove particles heavier than H+ from the beam. Voltage ratios across the lenses (14 and 16) and extraction electrodes (58 and 60) can be varied in tandem, permitting control over the final beam energy by a simple voltage adjustment. The beam is aligned with the column axis and then steered into alignment with the mask channeling axis by a pair of octupole lenses (13 and 30).

公开(公告)号：WO2003052803A1

公开(公告)日：2003-06-26

申请号：PCT/JP2002/012689

申请日：2002-12-04

Applicant: ソニー株式会社 ,  大森 真二 ,  守屋 茂

Inventor： 大森 真二 ,  守屋 茂

IPC: H01L21/027

CPC classification number: G03F1/20 ,  H01J2237/31788 ,  Y10S438/942

Abstract: A mask allowing an alignment of TTR method and a complementary division and having a high strength. A method for making the mask. A method for making semiconductor devices having high pattern accuracy. A stencil mask having, in four small regions (A-D) on a membrane, stripe beams (grids) (4) formed by etching a silicon wafer, wherein the stripes are symmetrically arranged about the center point of the membrane, and any one of the grids is connected to another grid or the silicon wafer around the periphery of the membrane (the support frame). A method for making the stencil mask. A method for making semiconductor devices by use of the stencil mask.

Abstract translation: 允许TTR方法和互补分割对齐并具有高强度的掩模。 一种制作掩模的方法。 一种制造具有高图案精度的半导体器件的方法。 在膜上的四个小区域（AD）中具有通过蚀刻硅晶片形成的条纹波束（栅格）（4））的模板掩模，其中所述条围绕所述膜的中心点对称设置，并且 栅格连接到另一个栅格或围绕膜周边的硅晶片（支撑框架）。 一种制作模板掩模的方法。 一种通过使用模板掩模制造半导体器件的方法。

公开(公告)号：WO2003046963A1

公开(公告)日：2003-06-05

申请号：PCT/JP2002/012505

申请日：2002-11-29

Applicant: ソニー株式会社 ,  納土 晋一郎 ,  小國 久美子 ,  中野 博之 ,  羽根 博樹

Inventor： 納土 晋一郎 ,  小國 久美子 ,  中野 博之 ,  羽根 博樹

IPC: H01L21/027

CPC classification number: G03F9/7046 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/20 ,  H01J37/3026 ,  H01J37/3045 ,  H01J37/3174 ,  H01J2237/3175 ,  H01J2237/31788 ,  Y10S430/143

Abstract: An exposure method and an exposure apparatus using a complementary division mask, wherein the alignment of the complementary division mask is achieved with high precision over all the regions of a semiconductor wafer. A semiconductor device made by the forgoing exposure method. A semiconductor device making method using the forgoing exposure method. In a first region of a central portion of a semiconductor wafer, the alignment of the complementary division mask is performed, based on the result of detecting the position of an alignment mark provided for each chip, by use of die−by−die alignment method, and then exposure is performed. In that second region outside the first region to which the alignment of the complementary division mask using the die−by−die alignment method cannot be applied, the coordinates of each chip in the second region are decided based on the result of detecting the positions of the alignment marks in the first process to perform the alignment of the complementary division mask by use of global alignment method, and then exposure is performed.

Abstract translation: 一种使用互补分割掩模的曝光方法和曝光装置，其中在半导体晶片的所有区域上以高精度实现互补分割掩模的对准。 通过上述曝光方法制造的半导体器件。 一种使用上述曝光方法的半导体器件制造方法。 在半导体晶片的中心部分的第一区域中，基于通过使用逐芯片对准方法检测每个芯片设置的对准标记的位置的结果，执行互补分割掩模的对准 ，然后进行曝光。 在不能应用使用逐芯片对准方法的互补分割掩模的对准的第一区域外的第二区域中，基于检测位置的结果来确定第二区域中的每个芯片的坐标 第一处理中的对准标记通过使用全局对准方法进行互补分割掩模的对准，然后进行曝光。