公开(公告)号：WO2007002802A1

公开(公告)日：2007-01-04

申请号：PCT/US2006/025300

申请日：2006-06-27

Applicant: QUALCOMM Incorporated ,  KOOB, Christopher Edward ,  LIANG, Jian

Inventor： KOOB, Christopher Edward ,  LIANG, Jian

IPC: G06F7/74

CPC classification number: G06F7/74 ,  G06F2207/3816

Abstract: A system and method is disclosed and includes an execution unit that can be used to count the leading zeros in a data word. During operation, the execution unit can receive a data word that has a width of 2 to the Nth power. Further, the execution unit can sign extend the data word to a temporary data word that has a width of 2 to the Mth power, wherein M is greater than N. The temporary data word can be input to a counter that has a width of 2 to the Mth power and the counter can count the leading zeros within the temporary data word to get a result.

Abstract translation: 公开了一种系统和方法，并且包括可用于对数据字中的前导零进行计数的执行单元。 在操作期间，执行单元可以接收宽度为2到第N次的数据字。 此外，执行单元可以将数据字符号扩展到具有2到第M个功率的宽度的临时数据字，其中M大于N.临时数据字可以被输入到宽度为2的计数器 到第M个功率，计数器可以计数临时数据字中的前导零，以获得结果。

公开(公告)号：WO2008121593A1

公开(公告)日：2008-10-09

申请号：PCT/US2008/057986

申请日：2008-03-24

Applicant: DSM SOLUTIONS, INC. ,  THUMMALAPALLY, Damodar, R.

Inventor： THUMMALAPALLY, Damodar, R.

IPC: G06F7/74 ,  G11C15/00

CPC classification number: G06F7/74

Abstract: A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating a highest-priority input signal that is asserted. The match module is also coupled to the plurality of input ports and receives a plurality of match detect signals from the priority encoding module. Each match detect signal is associated with a particular input signal and indicates whether another input signal having a higher-priority than the associated input signal is asserted. The match module also generates a multiple match signal based on the input signals and the match detect signals. The multiple match signal indicates whether more than one of the input signals is asserted.

Abstract translation: 用于识别有效信号的系统包括多个输入端口，优先级编码模块和匹配模块。 多个输入端口接收多个输入信号中的一个。 优先级编码模块耦合到多个输入端口，并且输出指示被断言的最高优先级输入信号的信号。 匹配模块还耦合到多个输入端口并且从优先级编码模块接收多个匹配检测信号。 每个匹配检测信号与特定输入信号相关联，并且指示是否断言具有比关联输入信号更高优先级的另一个输入信号。 匹配模块还基于输入信号和匹配检测信号生成多重匹配信号。 多重匹配信号指示多于一个输入信号是否被断言。

公开(公告)号：WO02029553A1

公开(公告)日：2002-04-11

申请号：PCT/GB2001/003744

申请日：2001-08-21

IPC: G06F7/00 ,  G06F7/50 ,  G06F7/505 ,  G06F7/74 ,  G06F7/76 ,  G06F9/30 ,  G06F9/302 ,  G06F9/305 ,  G06F9/315 ,  G06F9/38

CPC classification number: G06F7/505 ,  G06F7/49931 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F2207/3828

Abstract: A data processing system is provided with an instruction (ADD8T016) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in response to the same instruction. The instruction is well suited to use within systems having a data path (2) including a shifting circuit (6) upstream of an arithmetic circuit (8).

Abstract translation: 数据处理系统具有使用符号或零扩展来解开数据字的非相邻部分的指令（ADD8T016），并将其与单指令多数据类型算术运算（例如，在 对同一指令的回应。 该指令非常适合于在具有在运算电路（8）上游的移位电路（6）的数据路径（2）的系统内使用。

公开(公告)号：WO2014030257A1

公开(公告)日：2014-02-27

申请号：PCT/JP2012/071484

申请日：2012-08-24

Applicant: 富士通株式会社 ,  野村 義孝 ,  ▲葛▼ 毅

Inventor： 野村　義孝 ,  ▲葛▼　毅

IPC: G06F7/74

CPC classification number: G06F7/74

Abstract: 　正の値に変換された整数の演算結果における指定された範囲を切り出す切り出し位置指定部と、現在の入力データに対する切り出し範囲を決めるために、直前の入力データに対する整数の演算結果と、現在の入力データに対する整数の演算結果において、ビット単位の論理和演算を行う第１論理和演算部と、前記切り出し位置指定部の出力および前記第１論理和演算部の出力から、前記複数ブロックのデータに対する所定位置から連続する値を算出する算出部と、を有する。

Abstract translation: 该处理装置具有：切出位置指定单元，其切出转换为正值的整数的运算结果中的指定范围; 第一逻辑或运算单元，为了确定当前输入数据的切除范围，对先前输入数据的整数运算结果和当前输入数据的整数运算结果进行按位逻辑运算; 以及计算单元，其基于所述切出位置指定单元的输出和所述第一逻辑OR运算单元的输出，从多个块的数据的预定位置计算连续值。

公开(公告)号：WO2013150507A2

公开(公告)日：2013-10-10

申请号：PCT/IL2012/000147

申请日：2012-04-04

Applicant: VARONIS SYSTEMS, INC. ,  FAITELSON, Yakov ,  KORKUS, Ohad ,  BASS, David ,  KAYSAR, Yzhar ,  KRETZER-KATZIR, Ophir

Inventor： FAITELSON, Yakov ,  KORKUS, Ohad ,  BASS, David ,  KAYSAR, Yzhar ,  KRETZER-KATZIR, Ophir

IPC: G06F7/74

CPC classification number: G06F17/30997 ,  G06F17/30144

Abstract: An enterprise level data element review system including a data access event collection subsystem operative to collect data access event notifications relating to ones of a multiplicity of data elements, a data element metadata modification subassembly receiving an output from the data access event collection subsystem and providing a script indicating which data elements have had a metadata modification over a given period of time, and a data element dancer operative to collect at least one of metadata and access permissions for a plurality of data elements which is substantially less than the multiplicity of data elements and is selected on the basis of the script.

Abstract translation: 一种企业级数据元素审查系统，包括数据访问事件收集子系统，用于收集与多个数据元素中的一个相关的数据访问事件通知;数据元素元数据修改子组件，从数据访问事件收集子系统接收输出， 指示哪些数据元素在给定时间段内具有元数据修改的数据元素调节器，以及数据元素调节器，用于收集基本上小于多个数据元素的多个数据元素的元数据和访问许可中的至少一个， 是在脚本的基础上选择的。

公开(公告)号：WO2009134568A2

公开(公告)日：2009-11-05

申请号：PCT/US2009/038808

申请日：2009-03-30

Applicant: RAMBUS INC. ,  ABBASFAR, Aliazam

Inventor： ABBASFAR, Aliazam

IPC: G06F7/74

CPC classification number: H04L25/4908 ,  H03M5/145 ,  H04L25/14

Abstract: M-bit data are encoded into n-bit data such that the encoded n-bit data has a sufficient number of encoded data patterns enough to encode the number (2 m ) of data patterns in the m- bit data but that the n-bit data has Hamming Weights (HWs) with minimum (smallest possible) variation. Specifically, encoder logic is configured to receive 2 m of m-bit data patterns and encode the 2 m of m-bit data patterns to n-bit encoded data patterns, n being greater than m and me being a positive integer greater than one. The encoder logic is configured to map the 2 m m-bit data patterns to a subset of 2 n of the n-bit encoded data patterns, and the n-bit data patterns in said subset has a minimum (smallest possible) range of Hamming Weight variation while the number of the n-bit data patterns in said subset is not less than 2 m .

Abstract translation: M位数据被编码为n位数据，使得编码的n位数据具有足够数量的编码数据模式，足以对m位数据中的数据模式的数量（2m）进行编码，但是n位 数据具有最小（可能最小）变化的汉明重量（HW）。 具体地，编码器逻辑被配置为接收2m的m位数据模式，并将m位数据模式的2m编码为n位编码数据模式，n大于m，而我是大于1的正整数。 编码器逻辑被配置为将2m m位数据模式映射到n位编码数据模式的2n个子集，并且所述子集中的n位数据模式具有汉明权重变化的最小（最小可能）范围 而所述子集中的n位数据模式的数量不小于2m。

公开(公告)号：WO2009053962A2

公开(公告)日：2009-04-30

申请号：PCT/IL2008001238

申请日：2008-09-17

Applicant: DENSBITS TECHNOLOGIES LTD ,  WEINGARTEN HANAN

Inventor： WEINGARTEN HANAN

IPC: G06F7/74

CPC classification number: G11C29/82 ,  G06F11/1068 ,  G11C2029/0411

Abstract: A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

Abstract translation: 一种用于将至少一个闪存设备的集合中的多个逻辑页面存储的系统，每个闪存设备包括一组至少一个擦除块，所述系统包括用于基本上全部分发所述多个逻辑页面中的至少一个的装置 基本上所有闪存器件中的擦除块，从而为至少一个逻辑页定义其小页序列，其中包括逻辑页面上的所有信息，并且每个存储在擦除组中的不同擦除块内 块; 以及用于从多个逻辑页面中读取每个单独页面的装置，包括用于从该组擦除块中的不同擦除块调用和排序小页的序列的装置。

公开(公告)号：WO0137083A3

公开(公告)日：2002-01-10

申请号：PCT/US0031832

申请日：2000-11-16

Applicant: SUN MICROSYSTEMS INC

Inventor： SUDHARSANAN SUBRAMANIA ,  CHAN JEFFREY MENG WAH ,  TREMBLAY MARC

IPC: G06F7/74 ,  G06F9/308 ,  G06F9/315 ,  G06F9/30 ,  G06F7/00

CPC classification number: G06F7/74 ,  G06F9/30018 ,  G06F9/30032

Abstract: A method and apparatus for performing single-instruction bit field extraction and for counting a number of leading zeros in a sequence of bits on a general purpose processor are provided. The fast bit extraction operations are accomplished by executing a first instruction for extracting an arbitrary number of bits of a sequence of bits stored in two or more source registers of the processor starting at an arbitrary offset and the storing the extracted bits in a destination register. Both the source and the destination registers are specified by the instruction. In addition, a second instruction is provided for counting the number of leading zeros in a sequence of bits stored in two or more source registers of the processor and then storing a binary value representing the number of leading zeros in a destination register. Again the source and the destination registers are specified by the second instruction. Both the first and the second instructions are pipelined to obtain an effective throughput of one instruction every cycle, respectively. As a result, bit extraction operations are performed very efficiently by the processor, thereby reducing the overall processing time required to compress and decompress multimedia data.

Abstract translation: 提供了一种用于执行单指令位域提取并用于对通用处理器上的位序列中的前导零数进行计数的方法和装置。 快速位提取操作通过执行用于从任意偏移开始提取存储在处理器的两个或更多个源寄存器中的位序列的任意数量的比特并且将提取的比特存储在目的地寄存器中来实现。 源寄存器和目标寄存器均由指令指定。 此外，提供第二指令，用于对存储在处理器的两个或多个源寄存器中的位序列中的前导零的数目进行计数，然后将表示前导零数的二进制值存储在目的地寄存器中。 源和目标寄存器又由第二条指令指定。 第一和第二指令都被流水线分别获得每个周期一个指令的有效吞吐量。 结果，处理器非常有效地执行比特提取操作，从而减少压缩和解压多媒体数据所需的整体处理时间。

公开(公告)号：WO2022175075A1

公开(公告)日：2022-08-25

申请号：PCT/EP2022/052314

申请日：2022-02-01

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： JIVANESCU, Mihaela Andreea ,  GOMONY, Manil Dev ,  AIROLDI, Roberto ,  KANGAS, Marko Timo Juhani

IPC: G06F7/483 ,  G06F7/74

Abstract: Various example embodiments relate to computation of a shared exponent for numbers. A plurality of bit vectors may be obtained. A bitwise OR-operation may be performed for the plurality of bit vectors to obtain an auxiliary bit vector. The shared exponent may be then determined based on a position of a most significant bit having value equal to one in the auxiliary bit vector. The representation for the plurality of bit vectors may be then determined based on the shared exponent. Apparatuses, methods, and computer programs are disclosed.

公开(公告)号：WO2014124176A1

公开(公告)日：2014-08-14

申请号：PCT/US2014/015161

申请日：2014-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： HOFF, David Paul ,  DELLA ROVA, Tracey A. ,  MARTZLOFF, Jason P.

IPC: G06F7/74 ,  G11C15/04 ,  H03K19/00

CPC classification number: G11C15/04 ,  G06F7/74 ,  G11C15/043 ,  H03K19/0013

Abstract: The hybrid dynamic-static encoder described herein combines dynamic and static logic to provide area, power, and leakage savings relative to a fully dynamic encoder with an equivalent logic delay. For example, the hybrid dynamic-static encoder includes identical top and bottom halves, which are combined to produce final encoded index, hit, and multi-hit outputs. Each encoder half uses a dynamic net for each index bit with rows that match a search key dotted. If a row has been dotted to indicate that the row matches the search key, the dynamic nets associated therewith are evaluated to reflect the index associated with the row. Accordingly, the hybrid dynamic-static encoder has a reduced set of smaller dynamic nets that leverage redundant pull-down structures across the index, hit, and multi-hit dynamic nets.

Abstract translation: 这里描述的混合动态静态编码器结合动态和静态逻辑以相对于具有等效逻辑延迟的全动态编码器来提供面积，功率和泄漏节约。 例如，混合动态静态编码器包括相同的上半部分和下半部分，其被组合以产生最终编码索引，命中和多命中输出。 每个编码器一半使用每个索引位的动态网络，其中匹配搜索关键点的行。 如果已经点划线以指示该行与搜索关键字相匹配，则评估与之相关联的动态网络以反映与该行相关联的索引。 因此，混合动态静态编码器具有减少的较小动态网络的集合，其利用索引，命中和多命中动态网络的冗余下拉结构。