公开(公告)号：WO2021260792A1

公开(公告)日：2021-12-30

申请号：PCT/JP2020/024598

申请日：2020-06-23

Applicant: キオクシア株式会社

Inventor： 清水　敬 ,  福島　崇 ,  服巻　直美 ,  田原　寛子 ,  井手　謙一

IPC: H01L27/11582 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/53271 ,  H01L27/11556

Abstract: 実施形態の半導体記憶装置は、第１方向に積層された、それぞれタングステンを含む複数の第１導電体層と、前記複数の第１導電体層と交互に積層される積層部と、前記積層部に対して前記第１方向に直交する第２方向に突出する第１突出部とを含む複数の絶縁膜と、複数の前記積層部と前記複数の第１導電体層との積層体内を前記第１方向に延びる半導体層と、前記複数の第１導電体層と前記半導体層との間に配置される電荷蓄積層と、前記絶縁膜における前記第１突出部の上において前記第１導電体層に接して配置され、不純物を含むシリコンを有する複数の第２導電体層と、前記複数の第２導電体層のうちの１の第２導電体層の上に前記１の第２導電体に接して設けられ、導電性を有し、前記第１方向に延びる複数のコンタクトプラグと、を備える。

公开(公告)号：WO2021141876A1

公开(公告)日：2021-07-15

申请号：PCT/US2021/012141

申请日：2021-01-05

Applicant: APPLIED MATERIALS, INC.

Inventor： YOON, Byunghoon ,  GANGULI, Seshadri ,  CEN, Xi

IPC: C23C16/18 ,  C23C16/455 ,  C23C16/02 ,  C23C16/04 ,  H01L21/768 ,  C23C16/45534 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: Methods of depositing a metal film with high purity are discussed. A catalyst enhanced CVD process is utilized comprising an alkyl halide catalyst soak and a precursor exposure. The precursor comprises a metal precursor having the general formula (I): M-L1(L2)y, wherein M is a metal, L1 is an aromatic ligand, L2 is an aliphatic ligand, and y is a number in the range of from 2 to 8 to form a metal film on the substrate surface, wherein the L2 comprises 1,5-hexdiene, 1,4-hexadiene, and less than 5% of 1,3-hexadiene. Selective deposition of a metal film with high purity on a metal surface over a dielectric surface is described.

公开(公告)号：WO2022031492A1

公开(公告)日：2022-02-10

申请号：PCT/US2021/043441

申请日：2021-07-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： GREENLEE, Jordan, D. ,  KLEIN, Rita, J. ,  MCTEER, Everett, A. ,  HOPKINS, John, D. ,  LUO, Shuangqiang ,  TAN, Song, Kai ,  FONG, Jing, Wai ,  JINDAL, Anurag ,  QUEK, Chieh, Hsien

IPC: H01L27/11578 ,  H01L27/11575 ,  H01L27/11568 ,  H01L27/11551 ,  H01L27/11548 ,  H01L27/11521 ,  H01L21/8234 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53266 ,  H01L27/11582

Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.

公开(公告)号：WO2022240503A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/024105

申请日：2022-04-08

Applicant: APPLIED MATERIALS, INC.

Inventor： CEN, Xi ,  ZHAO, Mingrui ,  WANG, Peiqi ,  CHAN, Wei Min ,  WU, Kai ,  LUO, Yi ,  WU, Liqi

IPC: H01L21/285 ,  H01L21/768 ,  C23C16/02 ,  C23C16/04 ,  C23C16/06 ,  C23C16/52 ,  C23C16/0272 ,  C23C16/045 ,  C23C16/14 ,  C23C16/34 ,  C23C16/45536 ,  C23C16/45544 ,  C23C16/45557 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53266

Abstract: Embodiments herein are generally directed to methods of forming high aspect ratio metal contacts and/or interconnect features, e.g., tungsten features, in a semiconductor device. Often, conformal deposition of tungsten in a high aspect ratio opening results in a seam and/or void where the outward growth of tungsten from one or more walls of the opening meet. Thus, the methods set forth herein provide for a desirable bottom up tungsten bulk fill to avoid the formation of seams and/or voids in the resulting interconnect features, and provide an improved contact metal structure and method of forming the same. In some embodiments, an improved overburden layer or overburden layer structure is formed over the field region of the substrate to enable the formation of a contact or interconnect structure that has improved characteristics over conventionally formed contacts or interconnect structures.