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    薄膜晶体管及其制备方法
    2.
    发明申请
    薄膜晶体管及其制备方法 审中-公开

    公开(公告)号：WO2018196289A1

    公开(公告)日：2018-11-01

    申请号：PCT/CN2017/105993

    申请日：2017-10-13

    Applicant: 京东方科技集团股份有限公司

    Inventor： 顾鹏飞

    IPC: H01L21/336 ,  H01L29/786 ,  H01L29/34

    CPC classification number: H01L29/34 ,  H01L29/66742 ,  H01L29/786

    Abstract: 一种薄膜晶体管（100）及其制备方法，制备方法包括：形成有源层（110）；在有源层（110）上形成栅极绝缘层（120）；在栅极绝缘层（120）上形成栅极（130）；在栅极（130）上形成层间绝缘层（140）以覆盖栅极（130）和有源层（110），使得层间绝缘层（140）与有源层（110）之间的界面（180）具有施主类缺陷态；在层间绝缘层（140）中形成过孔（170）以暴露有源层（110）；以及在层间绝缘层（140）上形成源极（150）和漏极（160），使得源极（150）和漏极（160）分别通过过孔（170）与有源层（110）电连接。能够容易地使有源层局部导体化，从而降低源极/漏极与沟道区之间的电阻。

    DOPED SUBSTRATE TO BE HEATED
    4.
    发明申请
    DOPED SUBSTRATE TO BE HEATED 审中-公开
    待加料的基材

    公开(公告)号：WO2008120092A1

    公开(公告)日：2008-10-09

    申请号：PCT/IB2008/000780

    申请日：2008-03-25

    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  LANGER, Robert ,  LAHRECHE, Hacène

    Inventor： LANGER, Robert ,  LAHRECHE, Hacène

    IPC: H01L21/203 ,  H01L29/34

    CPC classification number: H01L29/34 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/0254 ,  H01L21/76254 ,  H01L29/36

    Abstract: The invention proposes a structure (10) intended to be heated comprising a substrate (11 ) for the front face (1 ) deposition of a useful layer intended to receive components for electronics, optics or optoelectronics, the structure (10) furthermore containing doped elements that absorb infrared radiation so as to substantially increase infrared absorption by the structure (10) so that said front face (1) reaches a given temperature when a given infrared power is supplied to the structure (10), characterized in that at least one part of the doped elements have insufficient electrical activity or localization in the structure, such that they cannot disturb the operation of the components. In addition, the invention relates to a method of producing this structure and a method of forming said useful layer in a semiconductor material on the structure.

    Abstract translation: 本发明提出了一种旨在被加热的结构（10），其包括用于正面（1）沉积用于电子，光学或光电子的部件的有用层的衬底（11），所述结构（10）还包含掺杂元素 其吸收红外辐射，以便基本上增加所述结构（10）的红外吸收，使得当向所述结构（10）提供给定的红外线功率时，所述前面（1）达到给定的温度，其特征在于，至少一个部分 的掺杂元件在结构中具有不足的电活动或定位，使得它们不能干扰部件的操作。 此外，本发明涉及一种制造该结构的方法以及在该结构上的半导体材料中形成该有用层的方法。

    GLASS INTERMETAL DIELECTRIC
    5.
    发明申请
    GLASS INTERMETAL DIELECTRIC 审中-公开
    玻璃纤维电介质

    公开(公告)号：WO1987002828A1

    公开(公告)日：1987-05-07

    申请号：PCT/US1986001733

    申请日：1986-08-25

    Applicant: MOTOROLA, INC.

    Inventor： MOTOROLA, INC. ,  TEODORSKI, John, F. ,  JEWETT-ENZMANN, Terri

    IPC: H01L29/34

    CPC classification number: H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An improved means and methods for forming multilayer metal electronic devices (10) where the intermetal dielectric (18) is formed of a three layer sandwich. The first metal layer (13) is covered with a dielectric layer (14) formed using plasma assisted oxide deposition or low pressure chemical vapor deposition. This first dielectric layer (14) is covered by a second dielectric layer (15) formed using a spun-on glass. The third dielectric layer (16) is formed by chemical vapor deposition or plasma deposition and is then covered with the second metal layer (17). Substantially improved step coverage is obtained and delamination between the intermetal dielectric (18) and the metal layers (13, 17) is avoided. The dielectric may be tapered-etched for contact holes.

    Abstract translation: 一种用于形成多层金属电子器件（10）的改进方法和方法，其中金属间电介质（18）由三层三明治形成。 第一金属层（13）用由等离子体辅助氧化物沉积或低压化学气相沉积形成的电介质层（14）覆盖。 第一电介质层（14）由使用纺丝玻璃形成的第二电介质层（15）覆盖。 第三电介质层（16）通过化学气相沉积或等离子体沉积形成，然后被第二金属层（17）覆盖。 获得了大幅提高的台阶覆盖率，避免了金属间电介质（18）与金属层（13,17）之间的分层。 电介质可以被锥形蚀刻用于接触孔。

    HIGH DENSITY FIBER-OPTIC MODULE WITH MULTI-FOLD FLEXIBLE CIRCUIT
    6.
    发明申请
    HIGH DENSITY FIBER-OPTIC MODULE WITH MULTI-FOLD FLEXIBLE CIRCUIT 审中-公开
    具有多层柔性电路的高密度光纤模块

    公开(公告)号：WO2004032203A3

    公开(公告)日：2004-05-27

    申请号：PCT/US0322461

    申请日：2003-07-16

    Applicant: EMCORE CORP

    Inventor： RATHNAM LAKSHMAN ,  LAU EDMOND ,  MERTZ PIERRE ,  YUEN ALBERT T ,  HUANG HOWARD

    IPC: G02B6/42 ,  H05K1/18 ,  G02B6/00 ,  G02B6/36 ,  H01L21/00 ,  H01L29/16 ,  H01L29/267 ,  H01L29/34

    CPC classification number: G02B6/4201 ,  G02B6/4256 ,  G02B6/4277 ,  G02B6/4281 ,  G02B6/4283 ,  H05K1/189 ,  H05K2201/10121

    Abstract: A flexible printed circuit board (FPCB) for fiber optic modules (200) includes a board with multiple bends, forming a structure with sides (306) and a bottom (303). The traces (204) in the FPCB traverse from the opto-electronic chips (210), through the sides of the FPCB, to the module (200) interconnects at the bottom (303). The multi-fold structure allows the FPCB to support a higher number of traces (204) than conventional single-fold FPCB's, and it allows the fanning out of signal traces from the opto-electronic and electronic chips (210) at the front of the fiber-optic module (200), thereby reducing the crosstalk between the traces. This higher number is provided with a FPCB that features a single insulating layer and without the need to criss-cross the traces (204), resulting in improved signal integrity over conventional multi-layer FPCB's.

    Abstract translation: 用于光纤模块（200）的柔性印刷电路板（FPCB）包括具有多个弯曲的板，形成具有侧面（306）和底部（303）的结构。 在FPCB中穿过FPCB的侧面的FPCB中的走线（204）在底部（303）互连。 多折叠结构允许FPCB支持比常规单折FPCB更多数量的迹线（204），并且其允许从在前面的光电子和电子芯片（210）的信号迹线扇出 光纤模块（200），从而减少迹线之间的串扰。 该更高数量的FPCB具有特征在于单个绝缘层并且不需要跨越迹线（204）的FPCB，导致比常规多层FPCB更好的信号完整性。

    ELECTRICALLY INACTIVE PASSIVATING LAYER FOR SEMICONDUCTOR DEVICES
    7.
    发明申请
    ELECTRICALLY INACTIVE PASSIVATING LAYER FOR SEMICONDUCTOR DEVICES 审中-公开
    用于半导体器件的电气非激活钝化层

    公开(公告)号：WO01095399A1

    公开(公告)日：2001-12-13

    申请号：PCT/US2001/016921

    申请日：2001-05-24

    IPC: H01L29/34 ,  H01L29/737 ,  H01L31/0304 ,  H01L31/11 ,  H01L33/44 ,  H01S5/028 ,  H01L31/0328 ,  H01L21/00 ,  H01L21/331 ,  H01L21/76 ,  H01L23/58 ,  H01L27/082 ,  H01L27/102 ,  H01L27/11 ,  H01L29/06 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L27/70

    CPC classification number: H01L33/44 ,  H01L29/34 ,  H01L29/7371 ,  H01L31/03046 ,  H01L31/1105 ,  H01S5/0282 ,  H01S2301/176 ,  Y02E10/544

    Abstract: Disclosed is a method and apparatus for passivating an active layer (505) of a semiconductor device to reduce surface recombination. A semi-insulating, semiconductor material (510) is deposited over the surface of the active layer of the semiconductor device. The semi-insulating material reduces surface recombination without adversely affecting the performance of the semiconductor device. The semi-insulating material may be any number of materials depending on the growth technique used. The semi-insulating material is preferably lattice-matched with the active layer to ensure an adequate bond between the two layers and preferably has an energy band gap that is higher than that of the active layer. The thickness of the semi-insulating material may vary depending upon the circuit fabrication process (515) and preferably has a thickness range of 100 to 1000 Angstroms.

    Abstract translation: 公开了一种用于钝化半导体器件的有源层（505）以减少表面复合的方法和装置。 半绝缘半导体材料（510）沉积在半导体器件的有源层的表面上。 半绝缘材料减少表面复合，而不会不利地影响半导体器件的性能。 半绝缘材料可以是任何数量的材料，这取决于所使用的生长技术。 半绝缘材料优选与有源层晶格匹配，以确保两层之间的适当接合，并且优选地具有比有源层高的能带隙。 半绝缘材料的厚度可以根据电路制造工艺（515）而变化，优选地具有100至1000埃的厚度范围。

    PASSIVATED SILICON SUBSTRATE
    8.
    发明申请
    PASSIVATED SILICON SUBSTRATE 审中-公开
    钝化硅基板

    公开(公告)号：WO1991011827A1

    公开(公告)日：1991-08-08

    申请号：PCT/US1991000392

    申请日：1991-01-22

    Applicant: COMMTECH INTERNATIONAL

    Inventor： COMMTECH INTERNATIONAL ,  MADOU, Marc, J.

    IPC: H01L29/34

    CPC classification number: H01L21/3144

    Abstract: A passivated silicon substrate structure (10) is set forth. A silicon substrate has a surface region (14) covered by a silicon dioxide layer (18) no more than about 1,000 Angstroms thick. A silicon oxynitride layer (20) of no more than about 300 Angstroms thick covers the silicon dioxide layer. The silicon oxynitride layer is produced by reaction of ammonia, hydrazine or methyl amine with an initially thicker silicon dioxide layer. A silicon nitride layer (22) covers the silicon oxynitride layer. The silicon nitride layer is at least about 250 Angstroms thick. It is produced by chemical vapor deposition. A passivation layer as set forth above provides electric insulation and is highly resistant to moisture attack.

    Abstract translation: 阐述钝化硅衬底结构（10）。 硅衬底具有由不超过约1,000埃厚的二氧化硅层（18）覆盖的表面区域（14）。 不超过约300埃厚的氧氮化硅层（20）覆盖二氧化硅层。 氧氮化硅层通过氨，肼或甲基胺与最初较厚的二氧化硅层的反应来制备。 氮化硅层（22）覆盖氮氧化硅层。 氮化硅层至少约250埃厚。 它是通过化学气相沉积生产的。 如上所述的钝化层提供电绝缘并且高度耐水分侵蚀。

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