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    SYNCHRONIZING SYSTEMS-ON-CHIP USING GPIO TIMESTAMPS
    1.
    发明申请
    SYNCHRONIZING SYSTEMS-ON-CHIP USING GPIO TIMESTAMPS 审中-公开

    公开(公告)号：WO2023059474A1

    公开(公告)日：2023-04-13

    申请号：PCT/US2022/044804

    申请日：2022-09-27

    Applicant: SNAP INC.

    Inventor： AHN, Samuel ,  RYUMA, Dmitry ,  ZHUANG, Richard

    IPC: G06F1/14 ,  G02B2027/0178 ,  G02B27/017 ,  G06F1/10 ,  G06F1/12 ,  G06F1/163 ,  G06F13/24 ,  G06F13/4068 ,  G06F2213/0026 ,  G06F2213/0038 ,  H04J3/065

    Abstract: An electronic eyewear device includes first and second systems-on-chip (SoCs) having independent time bases. The first and second SoCs are connected by a shared general purpose input/output (GPIO) connection and an inter-SoC interface. The first and second SoCs are synchronized to each other by the first SoC asserting the shared GPIO connection to the second SoC where assertion of the message to the shared GPIO connection triggers an interrupt request (IRQ) at the second SoC. The first SoC records a first timestamp for assertion of the message to the GPIO connection, and the second SoC records a second timestamp of receipt of the IRQ. The first SoC sends a message including the first timestamp to the second SoC over the inter-SoC interface. The second SoC calculates a clock offset between the first and second SoCs as a difference between the first and second timestamps.

    MMI 인터페이스 장치 및 그에 기반한 컴퓨팅 시스템
    2.
    发明申请
    MMI 인터페이스 장치 및 그에 기반한 컴퓨팅 시스템 审中-公开

    公开(公告)号：WO2022025318A1

    公开(公告)日：2022-02-03

    申请号：PCT/KR2020/010035

    申请日：2020-07-30

    Applicant: 김영일

    Inventor： 김영일 KIM, Young-il

    IPC: G06F13/42 ,  G06F13/16 ,  G06F13/24

    Abstract: 본 발명은 MMI 인터페이스 장치 및 그에 기반한 컴퓨팅 시스템에 관한 것이다. 제1 실시예에 따른 출력 MMI 인터페이스 장치는 마스터 프로세서와 슬레이브 프로세서 사이에 위치되어 비동기 방식으로 마스터 프로세서와 슬레이브 프로세서 간에 데이터를 교환하는 장치로서, 대용량의 데이터를 저장하는 제1 메모리 뱅크와; 대용량의 데이터를 저장하는 제2 메모리 뱅크; 및 제1 메모리 뱅크와 제2 메모리 뱅크 사이에 위치되며, 마스터 프로세서가 사용할 메모리 뱅크와 슬레이브 프로세서가 사용할 메모리 뱅크를 결정하고, 그 결정에 따라 제1 메모리 뱅크와 제2 메모리 뱅크에 버스를 각각 접속하여, 제1 메모리 뱅크와 제2 메모리 뱅크가 교대로 마스터 프로세서로부터 슬레이브 프로세서로 데이터를 출력하도록 하는 로테이션 버스 마스터(Rotation Bus Master)를 포함한다.

    INTERRUPT SIGNALING FOR A MEMORY DEVICE
    3.
    发明申请
    INTERRUPT SIGNALING FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：WO2021126656A1

    公开(公告)日：2021-06-24

    申请号：PCT/US2020/064238

    申请日：2020-12-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： BALB, Markus ,  HEIN, Thomas ,  HOENIGSCHMID, Heinz

    IPC: G06F13/24 ,  G06F11/10 ,  G06F13/42 ,  G01R31/3185 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Methods, systems, and devices for interrupt signaling for a memory device are described. A memory device may transmit an interrupt signal to a host device to alter a sequence of operations that would otherwise be executed by the host device. The memory device may transmit the interrupt signal in response to detecting an error condition at the memory device, a performance degradation at the memory device, or another trigger event. In some examples, the memory device may include a dedicated interrupt pin for transmitting interrupt signals. Alternatively, the memory device may transmit interrupt signals via a pin also sued to transmit error detection codes. For example, the memory device may transmit an interrupt signal before or after an error detection code or may invert the error detection code to indicate the interrupt, in which case the inverted error detection code may act as an interrupt signal.

    PROCESSOR AND INTERRUPT CONTROLLER THEREIN
    4.
    发明申请
    PROCESSOR AND INTERRUPT CONTROLLER THEREIN 审中-公开

    公开(公告)号：WO2021061514A1

    公开(公告)日：2021-04-01

    申请号：PCT/US2020/051446

    申请日：2020-09-18

    Applicant: ALIBABA GROUP HOLDING LIMITED

    Inventor： ZHAO, Chaojun ,  JIANG, Tao

    IPC: G06F13/18 ,  G06F13/20 ,  G06F13/24 ,  G06F13/26 ,  G06F15/16

    Abstract: The present invention discloses an interrupt controller, including: a sampling unit adapted to receive interrupts from various interrupt sources coupled to the interrupt controller and perform sampling on the received various interrupts; and a priority arbitration unit adapted to classify the received various interrupts into a plurality of interrupt segments, where each interrupt segment includes one or more sampled interrupts, and determine, segment by segment, an interrupt with the highest priority in a selected segment, until an interrupt with the highest priority among all interrupts is identified through arbitration and used as an to-be-responded-to interrupt. The present invention further discloses a processor including the interrupt controller, and a system-on-chip.

    一种服务器电源前后级通讯的方法、设备及可读介质
    5.
    发明申请
    一种服务器电源前后级通讯的方法、设备及可读介质 审中-公开

    公开(公告)号：WO2021027182A1

    公开(公告)日：2021-02-18

    申请号：PCT/CN2019/121106

    申请日：2019-11-27

    Applicant: 苏州浪潮智能科技有限公司

    Inventor： 赵燕燕

    IPC: G06F13/24 ,  G06F13/42

    Abstract: 一种服务器电源前后级通讯的方法，包括以下步骤：根据删除地址位的传输协议定时构建数据更新请求；打开串口发送中断并判断是否存在待传输的数据更新请求；响应于存在待传输的数据更新请求，通过串口发送中断将数据更新请求发送到前级并关闭串口发送中断；通过串口接收中断接收前级返回的数据。本发明还公开了一种计算机设备和可读存储介质。本发明提出的服务器电源前后级通讯的方法及装置有效解决服务器电源前后级的通讯问题，将前级的数据通过此方式更可靠的传输到后级并通过金手指反馈给BMC，提高电源的可靠性。

    SYSTEMS AND METHODS FOR STALLING HOST PROCESSOR
    7.
    发明申请
    SYSTEMS AND METHODS FOR STALLING HOST PROCESSOR 审中-公开

    公开(公告)号：WO2020097177A1

    公开(公告)日：2020-05-14

    申请号：PCT/US2019/060028

    申请日：2019-11-06

    Applicant: DOVER MICROSYSTEMS, INC.

    Inventor： MILBURN, Steven ,  SULLIVAN, Gregory, T.

    IPC: G06F21/12 ,  G06F9/30 ,  G06F9/48 ,  G06F13/16 ,  G06F13/24 ,  G06F21/52 ,  G06F21/55 ,  G06F21/56

    Abstract: Systems and methods for stalling a host processor. In some embodiments, the host processor may be caused to initiate one or more selected transactions, wherein the one or more selected transactions comprise a data bus transaction. The host processor may be prevented from completing the data bus transaction, to thereby stall the host processor, wherein: the act of causing the host processor to initiate one or more selected transactions comprises asserting an interrupt to cause the host processor to load, from an interrupt vector address, one or more instructions of an interrupt handler corresponding to the interrupt; the one or more instructions, when executed by the host processor, cause the host processor to check for a cause of the interrupt; and the act of preventing the host processor from completing the data bus transaction comprises preventing the host processor from checking for a cause of the interrupt.

    PROBE INTERRUPT DELIVERY
    8.
    发明申请
    PROBE INTERRUPT DELIVERY 审中-公开

    公开(公告)号：WO2020040874A1

    公开(公告)日：2020-02-27

    申请号：PCT/US2019/039288

    申请日：2019-06-26

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： KALYANASUNDHARAM, Vydhyanathan ,  MORTON, Eric Christopher ,  BROUSSARD, Bryan P. ,  MOYER, Paul James ,  WALKER, William Louie

    IPC: G06F13/24

    Abstract: Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

    SENSOR DEVICE AND METHOD
    10.
    发明申请
    SENSOR DEVICE AND METHOD 审中-公开
    传感器装置和方法

    公开(公告)号：WO2016209371A1

    公开(公告)日：2016-12-29

    申请号：PCT/US2016/030787

    申请日：2016-05-04

    Applicant: INTEL CORPORATION

    Inventor： KELLY, Mark ,  NOLAN, Keith ,  CARR, Hugh M. ,  O'BYRNE, Sean

    IPC: G06F1/26 ,  G06F13/40 ,  G06F13/42 ,  G06F13/24

    CPC classification number: G06F1/266 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

    Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that include a plurality of sensor connectors to removably receive a corresponding plurality of sensors and a power management module to selectively provide power to sensor connector power terminals in response to power management signals from a sensor control module. Other embodiments may be described and/or claimed.

    Abstract translation: 在实施例中，描述了包括多个传感器连接器以便可拆卸地接收相应的多个传感器的装置，方法和存储介质（暂时性和非暂时性的），以及电源管理模块，用于响应于 来自传感器控制模块的电源管理信号。 可以描述和/或要求保护其他实施例。

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