公开(公告)号：WO2016131719A1

公开(公告)日：2016-08-25

申请号：PCT/EP2016/053015

申请日：2016-02-12

Applicant: PHILIPS LIGHTING HOLDING B.V.

Inventor： LIU, Junhu ,  OP HET VELD, Johannes, Hubertus, Gerardus ,  WANG, Binghong ,  HATTRUP, Christian

IPC: G06G7/161 ,  G06G7/163 ,  H05B33/08

CPC classification number: H05B33/0815 ,  G06G7/161 ,  G06G7/163 ,  H05B33/0851 ,  Y02B20/346

Abstract: A level control circuit uses a reference voltage generated from a mains voltage signal by a reference circuit to provide a feedforward control signal. This control signal is used to generate a control signal for controlling a switched mode power converter. The reference circuit comprises a combining circuit adapted to apply a pulse width modulation control signal indicative of said level such that said reference voltage contains the level information. In an embodiment, the reference circuit comprises a voltage divider comprising a resistor circuit and the combining circuit comprises an adjustment module to which a pulse width modulation control signal is applied thereby to change the effective voltage divider ratio to implement level control. The level control further comprises a buffering capacitor or a buffered low pass filter coupled to the output (SET) of the voltage divider. This provides a power factor correction approach for active level control, and which can be implemented very simply and with low cost. It can be used for controlling lighting dimming.

Abstract translation: 电平控制电路使用由参考电路从电源电压信号产生的参考电压来提供前馈控制信号。 该控制信号用于产生用于控制开关模式功率转换器的控制信号。 参考电路包括组合电路，其适于施加指示所述电平的脉宽调制控制信号，使得所述参考电压包含电平信息。 在一个实施例中，参考电路包括一个分压器，该分压器包括一个电阻电路，该组合电路包括一个调整模块，脉宽调制控制信号被施加到该调整模块，从而改变有效分压比以实现电平控制。 电平控制还包括耦合到分压器的输出（SET）的缓冲电容器或缓冲低通滤波器。 这提供了用于主动电平控制的功率因数校正方法，其可以非常简单且成本低廉地实现。 可用于控制照明调光。

公开(公告)号：WO8904949A3

公开(公告)日：1989-11-02

申请号：PCT/US8803668

申请日：1988-10-19

Applicant: ANALOG DEVICES INC

Inventor： DEVITO LAWRENCE M ,  BROKAW A PAUL

IPC: G01D5/22 ,  G06G7/161

CPC classification number: G01D5/2266 ,  G01D5/2216 ,  G01D5/2291 ,  G06G7/161

Abstract: A monolithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to the LVDT primary winding. The interface circuit further includes a decoder responsive to signals induced in the LVDT secondary windings for computing the position p of the LVDT core as a solution to the equation p= K(A-B)/(A+B), where A and B represent the signals induced in the primary winding and K is a constant scale factor. The decoder includes circuitry for rectifying and filtering the secondary signals, a charge balance loop responsive to the detected signals for providing a binary signal having a duty cycle representative of B/(A+B), and an output circuit responsive to the binary signal for providing the position output. The decoder provides excellent scale factor stability and linearity and is relatively insensitive to variations in primary drive amplitude.

公开(公告)号：WO2020058885A1

公开(公告)日：2020-03-26

申请号：PCT/IB2019/057888

申请日：2019-09-19

Applicant: SENDYNE CORPORATION

Inventor： TSIVIDIS, Yannis

IPC: G06G7/161 ,  G06G7/66

Abstract: An improved integrator for use in physical analog-computing systems is disclosed, featuring real-time dynamic amplitude scaling schemas that make use of an injected correction factor responsive to a contemporaneous change in an input dynamic-amplitude-scaling compensation factor. The injected correction factor is designed to reduce or eliminate transient output perturbations due to the amplitude scaling change. The disclosures discussed have real-world applications for physical analog computers and hybrid computers used to control and manage many types of industrial-control systems.

公开(公告)号：WO2010118990A1

公开(公告)日：2010-10-21

申请号：PCT/EP2010/054705

申请日：2010-04-09

Applicant: STMicroelectronics (Research & Development) Ltd ,  DARZY, Saul

Inventor： DARZY, Saul

IPC: H03M1/06 ,  H03K9/08 ,  G06G7/161

CPC classification number: G06G7/161 ,  H03K9/08 ,  H03M1/0663 ,  H03M1/822

Abstract: A method of converting a periodic pulse width modulated input signal into a voltage output signal wherein the input signal is in an active state for a first portion of each of successive time periods and in an inactive state for a second portion of each time period. A first and second input is supplied to an integrator circuit and a first capacitor is coupled between a first output of the integrator circuit and the first input and a second capacitor is coupled between a second output and the second input of the integrator circuit during a first time period of the pulse width modulated signal. A third capacitor is coupled between a first output of the integrator circuit and the first input and a fourth capacitor is coupled between a second output of the integrator circuit and the second input during a successive second time period of the pulse width modulated signal. Said coupled capacitors are charged during the active state of the first and second time periods and discharged during the inactive state of the first and second time periods.

Abstract translation: 一种将周期性脉宽调制输入信号转换为电压输出信号的方法，其中输入信号对于每个连续时间段的第一部分处于活动状态，并且在每个时间周期的第二部分处于非活动状态。 第一和第二输入被提供给积分器电路，并且第一电容器耦合在积分器电路的第一输出端和第一输入端之间，第二电容器在第一和第二输入端之间耦合在第二输出端和积分器电路的第二输入端之间 脉宽调制信号的时间段。 第三电容器耦合在积分器电路的第一输出端和第一输入端之间，第四电容器在脉冲宽度调制信号的连续第二时间段期间耦合在积分器电路的第二输出端和第二输入端之间。 所述耦合电容器在第一和第二时间段的有效状态期间被充电，并且在第一和第二时间段的无效状态期间被放电。

公开(公告)号：WO2021228757A1

公开(公告)日：2021-11-18

申请号：PCT/EP2021/062305

申请日：2021-05-10

Applicant: UNIVERSITÄT STUTTGART

Inventor： GRÖZING, Markus

IPC: G06G7/16 ,  G06N3/063 ,  G06G7/161

Abstract: Die vorliegende Erfindung betrifft ein Verfahren zur analogen Multiplikation und/oder Berechnung eines Skalarprodukts mit einer Schaltungsanordnung, die eine Serienschaltung aus einem ersten FET und einem als Stromquelle dienenden zweiten FET oder FET-Array, eine Ladeeinrichtung und eine Kapazität aufweist, die über die Ladeeinrichtung vorgeladen und über die Serienschaltung aus dem ersten FET und dem zweiten FET oder FET-Array entladen werden kann. Die Kapazität wird hierbei zur Multiplikation eines ersten Wertes mit einem zweiten Wert zunächst vorgeladen. Der erste Wert wird als Pulslänge eines Spannungspulses kodiert an das Gate des ersten FET und der zweite Wert als Spannungsamplitude kodiert an das Gate des zweiten FET angelegt. Dadurch wird die Kapazität für den Zeitraum des Spannungspulses mit einem Entladungsstrom entladen, der durch die am zweiten FET anliegende Spannungsamplitude vorgegeben wird. Das Ergebnis der Multiplikation lässt sich dann aus der Restladung oder Restspannung der Kapazität bestimmen. Das Verfahren arbeitet sehr energieeffizient und lässt sich vorteilhaft für die Durchführung von Berechnungen in Neuronen eines künstlichen neuronalen Netzwerkes einsetzen.

公开(公告)号：WO2020153989A1

公开(公告)日：2020-07-30

申请号：PCT/US2019/043090

申请日：2019-07-23

Applicant: MICROSEMI SOC CORP.

Inventor： MCCOLLUM, John L. ,  GREENE, Jonathan W. ,  BAKKER, Gregory William

IPC: G06N3/063 ,  G06G7/161 ,  G06J1/00

Abstract: A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.

公开(公告)号：WO2012104707A3

公开(公告)日：2012-11-15

申请号：PCT/IB2012000147

申请日：2012-01-31

Applicant: UNIV CATALUNYA POLITECNICA ,  UNIV ROVIRA I VIRGILI ,  ALARCON COT EDUARD ,  RODRIGUEZ VILAMITJANA ENRIC ,  EL AROUDI CHAOUI ABDELALI

Inventor： ALARCON COT EDUARD ,  RODRIGUEZ VILAMITJANA ENRIC ,  EL AROUDI CHAOUI ABDELALI

IPC: H02M3/156 ,  G06G7/161 ,  H03F3/217

CPC classification number: H02M3/156 ,  H02M2001/0025

Abstract: The voltage-sensing circuit structure is intended to avoid fast-scale subharmonic instabilities in switching power converters, comprising a compact circuit structure to be connected at the output of a switching power converter, by means of which the sensed feedback voltage is altered with a double transfer function so that concurrently the ripple component is amplified to obtain an enhanced fast- scale stability margin while attenuating the converter output voltage ripple in the power path.

Abstract translation: 电压感测电路结构旨在避免开关功率转换器中的快速尺度分谐波不稳定性，其包括要在开关功率转换器的输出处连接的紧凑电路结构，借助于该小型电路结构，所感测的反馈电压被双倍 传递函数，使得同时纹波分量被放大以获得增强的快速尺度稳定裕度，同时衰减功率路径中的转换器输出电压纹波。

公开(公告)号：WO0223694A3

公开(公告)日：2003-09-18

申请号：PCT/US0128919

申请日：2001-09-13

Applicant: ARTESYN TECHNOLOGIES INC

Inventor： MARTINELLI ROBERT M

IPC: H02M7/12 ,  H02M1/00 ,  H02M1/42 ,  H02M3/155 ,  H02M1/12 ,  G06G7/161

CPC classification number: H02M1/4225 ,  Y02B70/126 ,  Y02P80/112

Abstract: A power factor correction circuit (22) for a boost power supply, wherein the boost power supply includes a boost converter responsive to a rectified AC line voltage. According to one embodiment, the power factor correction circuit includes a voltage feedback amplifier (40) having a first input terminal responsive to an output voltage of the boost converter, a switching multiplier circuit (46) having a first input terminal connected to an output terminal of the voltage feedback amplifier (48) and a second input terminal responsive to the rectified AC line voltage, a current feedback amplifier (48) having a first input terminal connected to an output terminal of the switching multiplier circuit and having a second input terminal responsive to an input current of the boost converter, and a pulse width modulator control circuit (20) having an input terminal connected to an output terminal of the current feedback amplifier (48) and having an output terminal for connection to a pulse width modulated switch of the boost converter.

Abstract translation: 一种用于升压电源的功率因数校正电路（22），其中所述升压电源包括响应于整流的AC线路电压的升压转换器。 根据一个实施例，功率因数校正电路包括具有响应于升压转换器的输出电压的第一输入端的电压反馈放大器（40），具有连接到输出端子的第一输入端的开关倍增器电路 电压反馈放大器（48）和响应于整流的AC线路电压的第二输入端子;电流反馈放大器（48），其具有连接到开关倍增器电路的输出端子的第一输入端子并具有响应于第二输入端子 与所述升压转换器的输入电流相关联，以及脉宽调制器控制电路（20），其具有连接到所述电流反馈放大器（48）的输出端的输入端，并具有用于连接到脉宽调制开关 升压转换器。