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    CLOCK SIGNAL RETURN SCHEME FOR DATA READ IN PAGE BUFFER OF MEMORY DEVICE
    3.
    发明申请
    CLOCK SIGNAL RETURN SCHEME FOR DATA READ IN PAGE BUFFER OF MEMORY DEVICE 审中-公开

    公开(公告)号：WO2022226820A1

    公开(公告)日：2022-11-03

    申请号：PCT/CN2021/090444

    申请日：2021-04-28

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： XIE, Shu

    IPC: G11C7/22

    Abstract: In certain aspects, a circuit includes a page buffer including a plurality of portions, a clock path coupled to the plurality of portions of the page buffer, and a clock level set module coupled to the page buffer. Each of the portions is configured to sequentially receive a clock signal, and sequentially return a clock return signal in response to receiving the corresponding clock signal. The clock path is configured to merge the plurality of clock return signals. The clock level set module is configured to set a start level of a first clock return signal of the plurality of clock return signals based on a number of cycles in a first clock signal of the plurality of clock signals. The first clock return signal corresponds to the first clock signal.

    读写窗口校准电路及方法、存储器、FPGA芯片
    4.
    发明申请
    读写窗口校准电路及方法、存储器、FPGA芯片 审中-公开

    公开(公告)号：WO2022141798A1

    公开(公告)日：2022-07-07

    申请号：PCT/CN2021/079686

    申请日：2021-03-09

    Applicant: 深圳市紫光同创电子有限公司

    Inventor： 潘超 ,  张勇 ,  温长清

    IPC: G11C7/22

    Abstract: 本申请实施例提供了一种读写窗口校准电路及方法、存储器、FPGA芯片，涉及集成电路技术领域，可以自动调节读窗口和写窗口，在读写窗口校准电路的工作频率满足预设频率的情况下，使读数据通过读窗口、写数据通过写窗口。该读写窗口校准电路包括：校准验证电路，在当前时钟周期内，验证读数据、写数据是否能通过读窗口写窗口；读写控制时序生成电路，当读数据不能通过读窗口时，增大读窗口，当写数据不能通过写窗口时，增大写窗口；校准验证电路，获取读写窗口校准电路的工作频率，当工作频率小于预设频率时，控制读写控制时序生成电路减小读窗口和/或所述写窗口，并在下一个时钟周期，重复验证读数据是否能通过读窗口、写数据是否能通过写窗口。

    VARIABLE CLOCK DIVIDER
    5.
    发明申请
    VARIABLE CLOCK DIVIDER 审中-公开

    公开(公告)号：WO2022055881A1

    公开(公告)日：2022-03-17

    申请号：PCT/US2021/049283

    申请日：2021-09-07

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： UEMURA, Yutaka

    IPC: H03K23/68 ,  H03K5/135 ,  G11C7/22

    Abstract: Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.

    MEMORY SUBSYSTEM CALIBRATION USING SUBSTITUTE RESULTS
    6.
    发明申请
    MEMORY SUBSYSTEM CALIBRATION USING SUBSTITUTE RESULTS 审中-公开

    公开(公告)号：WO2022031840A1

    公开(公告)日：2022-02-10

    申请号：PCT/US2021/044531

    申请日：2021-08-04

    Applicant: APPLE INC.

    Inventor： JETER, Robert E. ,  NOTANI, Rakesh L. ,  HSIUNG, Kai Lun ,  MALLADI, Venkata Ramana ,  RANJAN, Rahul ,  KORADA, Naveen Kumar

    IPC: G06F13/16 ,  G06F11/1076 ,  G06F13/1689 ,  G11C2207/2254 ,  G11C7/10 ,  G11C7/22

    Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

    NON-VOLATILE MEMORY DEVICE WITH STORED INDEX INFORMATION
    8.
    发明申请
    NON-VOLATILE MEMORY DEVICE WITH STORED INDEX INFORMATION 审中-公开

    公开(公告)号：WO2021055006A1

    公开(公告)日：2021-03-25

    申请号：PCT/US2020/022192

    申请日：2020-03-11

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： QIAN, Xiaozhou ,  PI, Xiao Yan ,  TIWARI, Vipin

    IPC: G11C16/16 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56 ,  G11C7/22

    Abstract: A memory device that includes a memory array having pluralities of non-volatile memory cells, a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells, and a controller. The controller is configured to erase the pluralities of non-volatile memory cells, set each of the index memory cells to a first state, and program first data into the memory array by reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state, programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and setting the first one of the index memory cells to a second state different from the first state.

    MULTI-PORTED NONVOLATILE MEMORY DEVICE WITH BANK ALLOCATION AND RELATED SYSTEMS AND METHODS
    9.
    发明申请
    MULTI-PORTED NONVOLATILE MEMORY DEVICE WITH BANK ALLOCATION AND RELATED SYSTEMS AND METHODS 审中-公开

    公开(公告)号：WO2021025853A1

    公开(公告)日：2021-02-11

    申请号：PCT/US2020/042808

    申请日：2020-07-20

    Applicant: CYPRESS SEMICONDUCTOR CORPORATION

    Inventor： BETSER, Yoram ,  ZITLAW, Cliff ,  ROSNER, Stephan ,  DANON, Kobi ,  ROCHMAN, Amir

    IPC: G11C7/10 ,  G11C7/22 ,  G06F13/16

    Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

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