- 专利标题: Lithography using high selectivity spacers for pitch reduction
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申请号: US15714821申请日: 2017-09-25
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公开(公告)号: US10014175B2公开(公告)日: 2018-07-03
- 发明人: Yu-Sheng Chang , Cheng-Hsiung Tsai , Chung-Ju Lee , Hai-Ching Chen , Hsiang-Huan Lee , Ming-Feng Shieh , Ru-Gun Liu , Shau-Lin Shue , Tien-I Bao , Tsai-Sheng Gau , Yung-Hsu Wu
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater Matsil, LLP
- 主分类号: H01L21/338
- IPC分类号: H01L21/338 ; H01L21/033 ; H01L21/02 ; H01L21/306 ; H01L21/3213
摘要:
A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
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