Invention Grant
- Patent Title: Semiconductor devices having vertical transistors with aligned gate electrodes
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Application No.: US15664226Application Date: 2017-07-31
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Publication No.: US10256324B2Publication Date: 2019-04-09
- Inventor: Sungil Park , Changhee Kim , Yunil Lee , Mirco Cantoro , Junggun You , Donghun Lee
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2017-0024948 20170224
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L21/28 ; H01L29/40 ; H01L29/423

Abstract:
A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.
Public/Granted literature
- US20180248018A1 Semiconductor Devices Having Vertical Transistors with Aligned Gate Electrodes Public/Granted day:2018-08-30
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