Method for searching matching key of storage device and server system including the same

    公开(公告)号:US10162568B2

    公开(公告)日:2018-12-25

    申请号:US15242642

    申请日:2016-08-22

    Abstract: A matching key search method of a server system including a storage device, the storage device including a nonvolatile memory device and a buffer memory. The matching key search method includes receiving a search command for a keyword from a host, reading data from a memory area of the memory device corresponding to an address included in the search command and storing the read data in the buffer memory, determining whether the read data matches the keyword, transmitting a result of the determining to the host without transmitting the read data to the host, and generating a matching key table with reference to the result of the determining and storing the generated matching key table in the buffer memory.

    Delay locked loop including a delay code generator

    公开(公告)号:US10305494B2

    公开(公告)日:2019-05-28

    申请号:US15599191

    申请日:2017-05-18

    Abstract: A delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween, and generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.

    SEMICONDUCTOR DEVICE
    9.
    发明申请

    公开(公告)号:US20250142814A1

    公开(公告)日:2025-05-01

    申请号:US18667445

    申请日:2024-05-17

    Abstract: A semiconductor device includes an interconnection line, an insulating layer on the interconnection line and having an opening exposing a top surface of the interconnection line, and a redistribution pattern extending into the opening and electrically connected to the interconnection line at a bottom surface of the opening. The interconnection line is configured to provide a current path in a first direction in a region adjacent to the redistribution pattern. The opening comprises a first side surface facing the first direction. A corner region of the opening protrudes away from or is recessed towards the opening at an end portion of the first side surface of the opening when viewed in plan view.

    MEMORY DEVICE PERFORMING OFFSET CALIBRATION AND OPERATING METHOD THEREOF

    公开(公告)号:US20250006233A1

    公开(公告)日:2025-01-02

    申请号:US18885337

    申请日:2024-09-13

    Abstract: Disclosed are a memory device that performs offset calibration and a method of operating the memory device. The memory device includes an input/output pad configured to receive data from a device external, an on-die termination (ODT) circuit connected to the input/output pad, a plurality of receivers connected to the ODT circuit and configured to receive the data from the input/output pad, an offset calibration circuit configured to perform an offset calibration operation on data output from the plurality of receivers and output an offset correction, a first switch configured to provide a first voltage to the plurality of receivers, and a second switch configured to provide a second voltage to the plurality of receivers. During the offset calibration operation, the plurality of receivers receive a third voltage in response to the ODT circuit being enabled and the first voltage through the first switch.

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