Invention Grant
- Patent Title: Coarse delay lock estimation for digital DLL circuits
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Application No.: US15089523Application Date: 2016-04-02
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Publication No.: US10270453B2Publication Date: 2019-04-23
- Inventor: Fangxing Wei , Khushal Chandan , Dan Shi , Michael Allen
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Thorpe North and Western, LLP
- Agent David W. Osborne
- Main IPC: H03L7/081
- IPC: H03L7/081 ; H03L7/091 ; G11C11/56 ; G11C7/14 ; H03L7/10
Abstract:
Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.
Public/Granted literature
- US20170288683A1 COARSE DELAY LOCK ESTIMATION FOR DIGITAL DLL CIRCUITS Public/Granted day:2017-10-05
Information query
