公开(公告)号：US20200007132A1

公开(公告)日：2020-01-02

申请号：US16392184

申请日：2019-04-23

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Khushal Chandan ,  Dan Shi ,  Michael Allen

IPC: H03L7/081 ,  H03L7/091 ,  G11C11/56 ,  G11C7/14 ,  H03L7/10

Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

公开(公告)号：US20170288683A1

公开(公告)日：2017-10-05

申请号：US15089523

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Khushal Chandan ,  Dan Shi ,  Michael Allen

IPC: H03L7/081 ,  G11C11/56 ,  G11C7/14 ,  H03L7/091

CPC classification number: H03L7/0814 ,  G11C7/14 ,  G11C11/56 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/091 ,  H03L7/10

Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

公开(公告)号：US11018676B2

公开(公告)日：2021-05-25

申请号：US16392184

申请日：2019-04-23

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Khushal Chandan ,  Dan Shi ,  Michael Allen

IPC: H03L7/08 ,  H03L7/081 ,  H03L7/091 ,  G11C11/56 ,  G11C7/14 ,  H03L7/10

Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

公开(公告)号：US10270453B2

公开(公告)日：2019-04-23

申请号：US15089523

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Khushal Chandan ,  Dan Shi ,  Michael Allen

IPC: H03L7/081 ,  H03L7/091 ,  G11C11/56 ,  G11C7/14 ,  H03L7/10

Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.