公开(公告)号：US11018676B2

公开(公告)日：2021-05-25

申请号：US16392184

申请日：2019-04-23

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Khushal Chandan ,  Dan Shi ,  Michael Allen

IPC: H03L7/08 ,  H03L7/081 ,  H03L7/091 ,  G11C11/56 ,  G11C7/14 ,  H03L7/10

Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

公开(公告)号：US10270453B2

公开(公告)日：2019-04-23

申请号：US15089523

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Khushal Chandan ,  Dan Shi ,  Michael Allen

IPC: H03L7/081 ,  H03L7/091 ,  G11C11/56 ,  G11C7/14 ,  H03L7/10

Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

公开(公告)号：US20170337952A1

公开(公告)日：2017-11-23

申请号：US15161908

申请日：2016-05-23

Applicant: Intel Corporation

Inventor： Dan Shi ,  Fangxing Wei ,  Michael J. Allen

IPC: G11C7/10 ,  G11C7/22 ,  H03K5/05 ,  H03K5/156

CPC classification number: G11C7/10 ,  G11C7/1072 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  G11C2211/4061 ,  H03K5/05 ,  H03K5/1565

Abstract: Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.

公开(公告)号：US10122526B2

公开(公告)日：2018-11-06

申请号：US15477078

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Dan Shi ,  Michael J. Allen

IPC: H04L7/033 ,  H04L7/027 ,  H04L7/04 ,  H03L7/087 ,  H04L7/00

Abstract: Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.

公开(公告)号：US09805773B1

公开(公告)日：2017-10-31

申请号：US15161908

申请日：2016-05-23

Applicant: Intel Corporation

Inventor： Dan Shi ,  Fangxing Wei ,  Michael J Allen

IPC: H03K5/156 ,  G11C7/10 ,  H03K5/05 ,  G11C7/22

CPC classification number: G11C7/10 ,  G11C7/1072 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  G11C2211/4061 ,  H03K5/05 ,  H03K5/1565

Abstract: Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.

公开(公告)号：US20200007132A1

公开(公告)日：2020-01-02

申请号：US16392184

申请日：2019-04-23

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Khushal Chandan ,  Dan Shi ,  Michael Allen

IPC: H03L7/081 ,  H03L7/091 ,  G11C11/56 ,  G11C7/14 ,  H03L7/10

Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

公开(公告)号：US20180287774A1

公开(公告)日：2018-10-04

申请号：US15477078

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Dan Shi ,  Michael J. Allen

IPC: H04L7/033 ,  H04L7/027 ,  H04L7/04 ,  H03L7/087 ,  H04L7/00

CPC classification number: H04L7/0331 ,  H03K5/26 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/089 ,  H04L7/0037 ,  H04L7/0045 ,  H04L7/027 ,  H04L7/04

Abstract: Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.

公开(公告)号：US20170288683A1

公开(公告)日：2017-10-05

申请号：US15089523

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Fangxing Wei ,  Khushal Chandan ,  Dan Shi ,  Michael Allen

IPC: H03L7/081 ,  G11C11/56 ,  G11C7/14 ,  H03L7/091

CPC classification number: H03L7/0814 ,  G11C7/14 ,  G11C11/56 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/091 ,  H03L7/10

Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.