Invention Grant
- Patent Title: 3D semiconductor device and system
-
Application No.: US15950169Application Date: 2018-04-11
-
Publication No.: US10388568B2Publication Date: 2019-08-20
- Inventor: Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist
- Applicant: Monolithic 3D Inc.
- Applicant Address: US CA San Jose
- Assignee: Monolithic 3D Inc.
- Current Assignee: Monolithic 3D Inc.
- Current Assignee Address: US CA San Jose
- Agency: Tran & Associates
- Main IPC: H01L21/822
- IPC: H01L21/822 ; H01L25/065 ; H01L21/683 ; H01L29/786 ; H01L29/78 ; H01L21/84 ; G11C29/00 ; G11C17/06 ; G11C16/04 ; H03K19/177 ; H03K19/0948 ; H03K17/687 ; H01L27/118 ; H01L27/112 ; H01L27/11 ; H01L27/108 ; H01L27/105 ; H01L27/092 ; H01L27/06 ; H01L27/02 ; H01L25/18 ; H01L21/762 ; H01L23/544 ; H01L23/36 ; G11C17/14 ; H01L21/8238 ; G11C5/02 ; G11C5/06 ; H01L27/1157 ; H01L27/11578 ; H03K19/00 ; G11C13/00 ; H01L23/00 ; H01L23/525 ; H01L23/48 ; H01L27/24 ; G11C29/02 ; G11C8/10 ; H01L23/367 ; H01L23/498 ; G11C17/16

Abstract:
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type.
Public/Granted literature
- US20180301380A1 3D SEMICONDUCTOR DEVICE AND SYSTEM Public/Granted day:2018-10-18
Information query
IPC分类: