Invention Grant
- Patent Title: Gate cut method
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Application No.: US15643940Application Date: 2017-07-07
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Publication No.: US10396206B2Publication Date: 2019-08-27
- Inventor: Ashish Kumar Jha , Haiting Wang , Wei Hong , Wei Zhao , Tae Jeong Lee , Zhenyu Hu
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Hoffman Warnick LLC
- Agent Francois Pagette
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/088 ; H01L21/3213 ; H01L21/8234 ; H01L21/311 ; H01L21/033 ; H01L21/02 ; H01L21/027 ; H01L21/321 ; H01L21/3105 ; H01L21/3205 ; H01L29/66 ; H01L21/475 ; H01L29/43 ; H01L27/02 ; H01L27/118

Abstract:
A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.
Public/Granted literature
- US20190013245A1 GATE CUT METHOD Public/Granted day:2019-01-10
Information query
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