公开(公告)号：US20190341448A1

公开(公告)日：2019-11-07

申请号：US15968968

申请日：2018-05-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emilie M.S. Bourjot ,  Julien Frougier ,  Yi Qi ,  Ruilong Xie ,  Hui Zang ,  Hsien-Ching Lo ,  Zhenyu Hu

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08

Abstract: Various aspects of the disclosure include nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, not just on the top and sides of the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects of the disclosure include nanosheet-FET structures having a bottom isolation to reduce parasitic S/D leakage to the substrate.

公开(公告)号：US20190131432A1

公开(公告)日：2019-05-02

申请号：US15795833

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Sang Woo Lim ,  Kyung-Bum Koo ,  Alina Vinslava ,  Pei Zhao ,  Zhenyu Hu ,  Hsien-Ching Lo ,  Joseph F. Shepard, JR. ,  Shesh Mani Pandey

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

公开(公告)号：US10083874B1

公开(公告)日：2018-09-25

申请号：US15467536

申请日：2017-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong Yu ,  Zhenyu Hu ,  Haiting Wang

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/3065

Abstract: A method of manufacturing a FinFET structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved.

公开(公告)号：US10083873B1

公开(公告)日：2018-09-25

申请号：US15613981

申请日：2017-06-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xing Zhang ,  Xinyuan Dou ,  Hong Yu ,  Zhenyu Hu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor structures with uniform gate heights and methods of manufacture. The structure includes: short channel devices in a first area of an integrated circuit die; and long channel devices in a second area of the integrated circuit die. The long channel devices have a same gate height as the short channel devices.

公开(公告)号：US09406676B2

公开(公告)日：2016-08-02

申请号：US14676165

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Jin Ping Liu

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the sacrificial gate structures is removed to define a first opening that exposes a portion of the fin. An etch process is performed through the first opening on the exposed portion of the fin to define a first recess in the fin. The first recess is filled with a dielectric material to define a diffusion break in the fin. A device includes a fin defined in a substrate, a plurality of gates formed above the fin, a plurality of recesses filled with epitaxial material defined in the fin, and a diffusion break defined at least partially in the fin between two of the recesses filled with epitaxial material and extending above the fin.

Abstract translation: 一种方法包括在半导体衬底中形成翅片。 在翅片上形成多个牺牲栅极结构。 去除所选择的牺牲栅极结构之一以限定暴露鳍片的一部分的第一开口。 通过翅片的暴露部分上的第一开口进行蚀刻处理，以限定翅片中的第一凹部。 第一凹部填充有电介质材料以限定散热片中的扩散断裂。 一种装置包括限定在衬底中的翅片，形成在鳍片上方的多个栅极，填充有限定在翅片中的外延材料的多个凹槽以及至少部分地限定在翅片中的两个凹槽之间的扩散断裂， 外延材料并在翅片上方延伸。

公开(公告)号：US09219002B2

公开(公告)日：2015-12-22

申请号：US14028724

申请日：2013-09-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Andy Wei ,  Qi Zhang ,  Richard J. Carter ,  Hongliang Shen ,  Daniel Pham ,  Sruthi Muralidharan

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/845 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Abstract translation: 提供了用于提高集成电路（IC）设备的覆盖性能的方法。 具体地，IC器件（例如，鳍式场效应晶体管（FinFET））设置有形成在衬底上的氧化物层和衬垫层，其中氧化物层包括取向和覆盖标记，沉积在一组 通过衬垫层并进入衬底形成的开口，沉积在氧化物材料和衬垫层上的心轴层，以及在IC器件中图案化的一组鳍片，而不蚀刻对准和重叠标记。 利用这种方法，对准和重叠标记设置有翅片切割（FC）层，因此避免了精细化。

公开(公告)号：US20150021695A1

公开(公告)日：2015-01-22

申请号：US13944048

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Richard J. Carter ,  Andy Wei ,  Qi Zhang ,  Sruthi Muralidharan ,  Amy L. Child

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

Abstract translation: 提供了在半导体器件（例如，鳍式场效应晶体管器件）的外延连接区域中实现均匀外延（epi）生长的方法。 具体地说，提供了一种半导体器件，包括形成在衬底上的伪栅极和一组鳍状场效应晶体管（FinFET）; 形成在所述伪栅极和所述一组FinFET中的每一个上的间隔层; 以及形成在衬底中的一组凹部内的外延材料，该组凹陷在去除伪栅极之前的外延阻挡层之前形成。

公开(公告)号：US08846491B1

公开(公告)日：2014-09-30

申请号：US13921377

申请日：2013-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Pham ,  Zhenyu Hu ,  Andy Wei ,  Nicholas V. LiCausi

IPC: H01L21/76 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/02104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments herein provide approaches for forming a diffusion break during a replacement metal gate process. Specifically, a semiconductor device is provided with a set of replacement metal gate (RMG) structures over a set of fins patterned from a substrate; a dielectric material over an epitaxial junction area; an opening formed between the set of RMG structures and through the set of fins, wherein the opening extends through the dielectric material, the expitaxial junction area, and into the substrate; and silicon nitride (SiN) deposited within the opening to form the diffusion break.

Abstract translation: 本文的实施例提供了在替换金属浇口工艺期间形成扩散断裂的方法。 具体而言，半导体器件在从衬底图案化的一组鳍片上设置有一组置换金属栅极（RMG）结构; 在外延结区上的电介质材料; 所述开口形成在所述一组RMG结构之间并且穿过所述一组翅片，其中所述开口延伸穿过所述电介质材料，所述外延结结区域并进入所述基板; 和沉积在开口内的氮化硅（SiN）以形成扩散断裂。

公开(公告)号：US10777642B2

公开(公告)日：2020-09-15

申请号：US16262105

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  George R. Mulfinger ,  Hui Zang ,  Liu Jiang ,  Zhenyu Hu

IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.

公开(公告)号：US10121788B1

公开(公告)日：2018-11-06

申请号：US15873006

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hong Yu ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu

IPC: H01L21/84 ,  H01L27/088 ,  H01L21/02 ,  H01L21/308 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.