Invention Grant
- Patent Title: Rlink—die to die channel interconnect configurations to improve signaling
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Application No.: US16305012Application Date: 2016-07-02
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Publication No.: US10784204B2Publication Date: 2020-09-22
- Inventor: Kemal Aygun , Richard J. Dischler , Jeff C. Morriss , Zhiguo Qian , Wilfred Gomes , Yu Amos Zhang , Ram S. Viswanath , Rajasekaran Swaminathan , Sriram Srinivasan , Yidnekachew S. Mekonnen , Sanka Ganesan , Eduard Roytman , Mathew J. Manusharow
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/040912 WO 20160702
- International Announcement: WO2018/009171 WO 20180111
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/522 ; H01L23/528 ; H01L23/60 ; H01L23/00 ; H01L25/065

Abstract:
Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
Public/Granted literature
- US20200066641A1 RLINK - DIE TO DIE CHANNEL INTERCONNECT CONFIGURATIONS TO IMPROVE SIGNALING Public/Granted day:2020-02-27
Information query
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