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    REPLACEABLE ON-PACKAGE MEMORY DEVICES
    3.
    发明申请
    REPLACEABLE ON-PACKAGE MEMORY DEVICES 审中-公开

    公开(公告)号：US20190182955A1

    公开(公告)日：2019-06-13

    申请号：US15841246

    申请日：2017-12-13

    申请人： Intel Corporation

    发明人： Gregorio R. Murtagian ,  Kuang C. Liu ,  Sriram Srinivasan ,  Jeffory L. Smalley ,  Zhichao Zhang

    IPC分类号： H05K1/14 ,  H01R12/73 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02 ,  H05K3/36 ,  H05K3/34

    摘要： Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate. The electronic device package can also include a processor mounted on the package substrate. Additionally, the electronic device package can include a memory socket mounted on the package substrate and operably coupled to the processor. The memory socket can be operable to removably couple with a memory module and facilitate electrical communication between the processor and the memory module. A memory module can include a plurality of printed circuit boards (PCBs). Each PCB can have a bottom edge and a plurality of contact pads located about the bottom edge. Additionally, the memory module can include a memory device mounted on at least one of the plurality of PCBs and electrically connected to at least one of the pluralities of contact pads to facilitate electrically coupling the memory module with an external electronic component, such as a processor. Associated systems and methods are also disclosed.

    MICROELECTRONIC ASSEMBLIES INCLUDING BRIDGES
    8.
    发明申请
    MICROELECTRONIC ASSEMBLIES INCLUDING BRIDGES 有权

    公开(公告)号：US20230086691A1

    公开(公告)日：2023-03-23

    申请号：US17482681

    申请日：2021-09-23

    申请人： Intel Corporation

    发明人： Sriram Srinivasan ,  Sanka Ganesan ,  Timothy A. Gosselin

    IPC分类号： H01L23/538 ,  H01L21/48

    摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a microelectronic subassembly including a first bridge component in a first layer, the first bridge component having a first surface and an opposing second surface, and a die in a second layer, wherein the second layer is on the first layer, and the die is electrically coupled to the second surface of the first bridge component; a package substrate having a second bridge component embedded therein, wherein the second bridge component is electrically coupled to the first surface of the first bridge component; and a microelectronic component on the second surface of the package substrate and electrically coupled to the second bridge component, wherein the microelectronic component is electrically coupled to the die via the first and second bridge components.

    PACKAGING ARCHITECTURE FOR DISAGGREGATED INTEGRATED VOLTAGE REGULATORS
    9.
    发明申请
    PACKAGING ARCHITECTURE FOR DISAGGREGATED INTEGRATED VOLTAGE REGULATORS 有权

    公开(公告)号：US20230060727A1

    公开(公告)日：2023-03-02

    申请号：US17412810

    申请日：2021-08-26

    申请人： Intel Corporation

    发明人： Kaladhar Radhakrishnan ,  Krishna Bharath ,  William J. Lambert ,  Adel A. Elsherbini ,  Sriram Srinivasan ,  Christopher Schaef

    IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

    摘要： A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.