公开(公告)号：US12087731B2

公开(公告)日：2024-09-10

申请号：US18127539

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Ram S. Viswanath ,  Nicholas Neal ,  Mitul Modi

IPC: H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US11901299B2

公开(公告)日：2024-02-13

申请号：US18079753

申请日：2022-12-12

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US10424561B2

公开(公告)日：2019-09-24

申请号：US15863821

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee ,  Islam A. Salama ,  Ram S. Viswanath ,  Robert L. Sankman ,  Babak Sabi ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/48 ,  H01L25/10 ,  H01L23/498 ,  H01L25/065

Abstract: An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.

公开(公告)号：US09832876B2

公开(公告)日：2017-11-28

申请号：US14575775

申请日：2014-12-18

Applicant: INTEL CORPORATION

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01L23/00 ,  H01R12/71 ,  H01R12/79

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

公开(公告)号：US10187996B2

公开(公告)日：2019-01-22

申请号：US15459787

申请日：2017-03-15

Applicant: Intel Corporation

Inventor： Rajasekaran Swaminathan ,  Ram S. Viswanath

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/00 ,  H05K3/30 ,  H05K3/46

Abstract: Embodiments of the present disclosure provide techniques for a printed circuit board (PCB) with a recess to accommodate discrete components of a package attachable to the PCB, in accordance with some embodiments. In one embodiment, a PCB may include a recess disposed in at least a portion of the PCB, to receive at least a portion of a package. The package may be attachable to the PCB via a plurality of connectors. The connectors may be disposed on a side of the package that faces the PCB. The portion of the package may include one or more discrete components disposed on the side of the package that faces the PCB. The recess may have a depth to accommodate those discrete components that have a height that is greater than a height of the connectors. Other embodiments may be described and/or claimed.

公开(公告)号：US09265170B2

公开(公告)日：2016-02-16

申请号：US14065281

申请日：2013-10-28

Applicant: INTEL CORPORATION

Inventor： Rajasekaran Swaminathan ,  Ram S. Viswanath ,  Sanka Ganesan ,  Gaurav Chawla ,  Joshua D. Heppner ,  Jeffory L. Smalley ,  Vijaykumar Krithivasan ,  David J. Llapitan ,  Neal E. Ulen ,  Donald T. Tran

IPC: H01R12/00 ,  H05K1/00 ,  H05K7/10 ,  H01R12/71 ,  H01R13/24

CPC classification number: H05K7/10 ,  H01R12/00 ,  H01R12/716 ,  H01R13/2442 ,  H05K1/00 ,  Y10T29/49169

Abstract: Embodiments related to integrated circuit (IC) connectors are described. In some embodiments, an IC assembly may include an IC package substrate, an intermediate member, and a male connector. The IC package substrate may have first signal contacts on a top or bottom surface, and the bottom surface may have second signal contacts for coupling with a socket on a circuit board. The intermediate member may have a first end coupled to the first signal contacts and a second end extending beyond the side surface. The male connector may be disposed at the second end of the intermediate member, and may have signal contacts coupled to the signal contacts of the intermediate member. The male connector may be mateable with a female connector when the female connector is brought into engagement in a direction parallel to the axis of the intermediate member. Other embodiments may be disclosed and/or claimed.

Abstract translation: 描述了与集成电路（IC）连接器相关的实施例。 在一些实施例中，IC组件可以包括IC封装衬底，中间构件和阳连接器。 IC封装基板可以在顶表面或底表面上具有第一信号触点，并且底表面可以具有用于与电路板上的插座耦合的第二信号触点。 中间构件可以具有联接到第一信号触头的第一端和延伸超过侧表面的第二端。 阳连接器可以设置在中间构件的第二端处，并且可以具有联接到中间构件的信号触点的信号触点。 当阴连接器沿平行于中间构件的轴线的方向接合时，阳连接器可与母连接器配合。 可以公开和/或要求保护其他实施例。

公开(公告)号：US10784204B2

公开(公告)日：2020-09-22

申请号：US16305012

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Richard J. Dischler ,  Jeff C. Morriss ,  Zhiguo Qian ,  Wilfred Gomes ,  Yu Amos Zhang ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Sriram Srinivasan ,  Yidnekachew S. Mekonnen ,  Sanka Ganesan ,  Eduard Roytman ,  Mathew J. Manusharow

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/528 ,  H01L23/60 ,  H01L23/00 ,  H01L25/065

Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

公开(公告)号：US20140217571A1

公开(公告)日：2014-08-07

申请号：US13996498

申请日：2011-12-20

Applicant: INTEL CORPORATION

Inventor： Sanka Ganesan ,  Ram S. Viswanath

IPC: H01L23/00 ,  H01B7/04

CPC classification number: H01R12/79 ,  H01B7/04 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/72 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01R12/62 ,  H05K1/142 ,  H05K1/147 ,  H05K3/361 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10424 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2201/2009 ,  H01L2224/0401

Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.

Abstract translation: 介绍了一种集成电路封装。 在一个实施例中，集成电路封装具有形成在封装基板的顶侧上的接触焊盘，电连接到接触焊盘的管芯，以及形成在封装基板的顶侧上的输入/输出（I / O）焊盘。 I / O焊盘电连接到接触焊盘。 集成电路封装还包括电连接到封装衬底的顶侧上的I / O焊盘的挠性电缆插座。 柔性电缆插座不可压缩地附接到柔性电缆连接器，并且包括电连接到I / O焊盘的插座连接引脚。

公开(公告)号：US20180270957A1

公开(公告)日：2018-09-20

申请号：US15459787

申请日：2017-03-15

Applicant: Intel Corporation

Inventor： Rajasekaran Swaminathan ,  Ram S. Viswanath

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/00 ,  H05K3/30 ,  H05K3/46

CPC classification number: H05K1/183 ,  H05K1/0216 ,  H05K1/113 ,  H05K1/141 ,  H05K3/0014 ,  H05K3/303 ,  H05K3/46 ,  H05K3/4697 ,  H05K2201/09036 ,  H05K2201/09072 ,  H05K2201/10628 ,  H05K2201/10719 ,  H05K2201/10734

Abstract: Embodiments of the present disclosure provide techniques for a printed circuit board (PCB) with a recess to accommodate discrete components of a package attachable to the PCB, in accordance with some embodiments. In one embodiment, a PCB may include a recess disposed in at least a portion of the PCB, to receive at least a portion of a package. The package may be attachable to the PCB via a plurality of connectors. The connectors may be disposed on a side of the package that faces the PCB. The portion of the package may include one or more discrete components disposed on the side of the package that faces the PCB. The recess may have a depth to accommodate those discrete components that have a height that is greater than a height of the connectors. Other embodiments may be described and/or claimed.

公开(公告)号：US09865568B2

公开(公告)日：2018-01-09

申请号：US15038008

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee ,  Islam A. Salama ,  Ram S. Viswanath ,  Robert L. Sankman ,  Babak Sabi ,  Sri Chaitra Jyotsna Chavali

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/11 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311

Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.