Invention Grant
- Patent Title: Dual metal gate structures for advanced integrated circuit structure fabrication
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Application No.: US16908468Application Date: 2020-06-22
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Publication No.: US10854732B2Publication Date: 2020-12-01
- Inventor: Jeffrey S. Leib , Jenny Hu , Anindya Dasgupta , Michael L. Hattendorf , Christopher P. Auth
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L27/24
- IPC: H01L27/24 ; G11C13/00 ; H01L45/00 ; G11C7/04 ; H01L29/66 ; H01L29/78 ; H01L27/088 ; H01L21/762 ; H01L29/06 ; H01L21/8234 ; H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L29/165 ; H01L29/417 ; H01L21/033 ; H01L21/28 ; H01L21/285 ; H01L21/308 ; H01L21/311 ; H01L21/8238 ; H01L23/528 ; H01L27/092 ; H01L27/11 ; H01L49/02 ; H01L29/08 ; H01L29/51 ; H01L27/02 ; H01L21/02 ; H01L29/167 ; H01L23/00

Abstract:
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.
Public/Granted literature
- US20200321449A1 DUAL METAL GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION Public/Granted day:2020-10-08
Information query
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