Invention Grant
- Patent Title: Asymmetric electronic substrate and method of manufacture
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Application No.: US16819899Application Date: 2020-03-16
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Publication No.: US10980129B2Publication Date: 2021-04-13
- Inventor: Sri Chaitra Jyotsna Chavali , Amruthavalli Pallavi Alur , Wei-Lun Kane Jen , Sriram Srinivasan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H05K1/09 ; H05K1/11 ; H05K1/16 ; H05K1/18 ; H05K3/00 ; H05K3/02 ; H05K3/04 ; H05K3/10 ; H05K3/20 ; H05K3/30 ; H05K3/36 ; H05K3/40 ; H05K3/42 ; H05K3/44 ; H05K3/46

Abstract:
An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.
Public/Granted literature
- US20200221577A1 ASYMMETRIC ELECTRONIC SUBSTRATE AND METHOD OF MANUFACTURE Public/Granted day:2020-07-09
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