Invention Grant
- Patent Title: Memory arrays and methods used in forming a memory array and conductive through-array-vias (TAVs)
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Application No.: US17367990Application Date: 2021-07-06
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Publication No.: US11705385B2Publication Date: 2023-07-18
- Inventor: Indra V. Chary , Chet E. Carter , Anilkumar Chandolu , Justin B. Dorhout , Jun Fang , Matthew J. King , Brett D. Lowe , Matthew Park , Justin D. Shepherdson
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- The original application number of the division: US16444634 2019.06.18
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/311 ; H01L21/033 ; H01L21/768 ; H01L21/28 ; H10B43/10 ; H10B43/27 ; H10B41/10 ; H10B41/27
Abstract:
A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.
Public/Granted literature
- US20210343624A1 Memory Arrays And Methods Used In Forming A Memory Array And Conductive Through-Array-Vias (TAVs) Public/Granted day:2021-11-04
Information query
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