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公开(公告)号：US12040253B2
公开(公告)日：2024-07-16
申请号：US17508143
申请日：2021-10-22
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , John D. Hopkins , Chet E. Carter , Justin D. Shepherdson , Collin Howder , Joshua Wolanyk
CPC classification number: H01L23/481 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. A through-array-via (TAV) region comprises TAVs that individually extend through the lowest conductive tier and into the conductor tier. Individual of the TAVs in the lowest conductive tier comprise a conductive core having an annulus circumferentially there-about. The annulus has dopant therein at a total dopant concentration of 0.01 to 30 atomic percent. Insulative material in the lowest conductive tier is circumferentially about the annulus and between immediately-adjacent of the TAVs. Other embodiments, including method, are disclosed.
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公开(公告)号：US20230389318A1
公开(公告)日：2023-11-30
申请号：US18359792
申请日：2023-07-26
Applicant: Micron Technology, Inc.
Inventor： Collin Howder , Justin D. Shepherdson , Chet E. Carter
Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.
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3.发明授权公开(公告)号：US11705385B2
公开(公告)日：2023-07-18
申请号：US17367990
申请日：2021-07-06
Applicant: Micron Technology, Inc.
Inventor： Indra V. Chary , Chet E. Carter , Anilkumar Chandolu , Justin B. Dorhout , Jun Fang , Matthew J. King , Brett D. Lowe , Matthew Park , Justin D. Shepherdson
IPC: H01L23/48 , H01L21/311 , H01L21/033 , H01L21/768 , H01L21/28 , H10B43/10 , H10B43/27 , H10B41/10 , H10B41/27
CPC classification number: H01L23/481 , H01L21/0337 , H01L21/31111 , H01L21/76897 , H01L29/40117 , H10B43/10 , H10B43/27 , H10B41/10 , H10B41/27
Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.
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公开(公告)号：US20230005956A1
公开(公告)日：2023-01-05
申请号：US17941900
申请日：2022-09-09
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Justin D. Shepherdson , Collin Howder , Jordan D. Greenlee
IPC: H01L27/11582 , H01L27/11556 , H01L21/02 , H01L27/11565 , H01L21/311 , H01L21/285 , H01L27/11519 , H01L29/66 , H01L21/28
Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.
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公开(公告)号：US11538822B2
公开(公告)日：2022-12-27
申请号：US16445065
申请日：2019-06-18
Applicant: Micron Technology, inc.
Inventor： John D. Hopkins , Justin D. Shepherdson , Collin Howder , Jordan D. Greenlee
IPC: H01L27/11582 , H01L27/11556 , H01L21/02 , H01L27/11565 , H01L21/311 , H01L21/285 , H01L27/11519 , H01L29/66 , H01L21/28
Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.
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Patent Agency Ranking
公开(公告)号：US20220336485A1
公开(公告)日：2022-10-20
申请号：US17233158
申请日：2021-04-16
Applicant: Micron Technology, Inc.
Inventor： Collin Howder , Justin D. Shepherdson , Chet E. Carter
IPC: H01L27/11578 , H01L27/11575 , H01L25/065
Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.
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7.发明授权公开(公告)号：US11069598B2
公开(公告)日：2021-07-20
申请号：US16444634
申请日：2019-06-18
Applicant: Micron Technology, Inc.
Inventor： Indra V. Chary , Chet E. Carter , Anilkumar Chandolu , Justin B. Dorhout , Jun Fang , Matthew J. King , Brett D. Lowe , Matthew Park , Justin D. Shepherdson
IPC: H01L23/48 , H01L27/11582 , H01L27/11565 , H01L21/311 , H01L21/033 , H01L21/768 , H01L21/28 , H01L27/11556 , H01L27/11519
Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.
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公开(公告)号：US12288585B2
公开(公告)日：2025-04-29
申请号：US17396056
申请日：2021-08-06
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , John D. Hopkins , Purnima Narayanan , Vinayak Shamanna , Justin D. Shepherdson
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating conductive tiers and insulative tiers. The stack comprises laterally-spaced memory-block regions. The lower portion comprises multiple lower of the conductive tiers and multiple lower of the insulative tiers. The lower insulative tiers comprise insulative material. The lower conductive tiers comprise sacrificial material that is of different composition from that of the insulative material. The sacrificial material is replaced with conducting material. After the replacing of the sacrificial material, the vertically-alternating conductive tiers and insulative tiers of an upper portion of the stack are formed above the lower portion. The upper portion comprises multiple upper of the conductive tiers and multiple upper of the insulative tiers. The upper insulative tiers comprise insulating material. The upper conductive tiers comprise sacrifice material that is of different composition from that of the conducting material, the insulating material, and the insulative material. The sacrifice material is replaced with conductive material. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号：US11737275B2
公开(公告)日：2023-08-22
申请号：US17233158
申请日：2021-04-16
Applicant: Micron Technology, Inc.
Inventor： Collin Howder , Justin D. Shepherdson , Chet E. Carter
Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.
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公开(公告)号：US20230062403A1
公开(公告)日：2023-03-02
申请号：US17508143
申请日：2021-10-22
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , John D. Hopkins , Chet E. Carter , Justin D. Shepherdson , Collin Howder , Joshua Wolanyk
IPC: H01L23/48 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. A through-array-via (TAV) region comprises TAVs that individually extend through the lowest conductive tier and into the conductor tier. Individual of the TAVs in the lowest conductive tier comprise a conductive core having an annulus circumferentially there-about. The annulus has dopant therein at a total dopant concentration of 0.01 to 30 atomic percent. Insulative material in the lowest conductive tier is circumferentially about the annulus and between immediately-adjacent of the TAVs. Other embodiments, including method, are disclosed.
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